xmega a3u - Elfa

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XMEGA A3U 1. Ordering Information Ordering code Flash (bytes) EEPROM (bytes) SRAM (bytes) Speed (MHz) Power supply Package (1)(2)(3) Temp. ATxmega256A3U-AU 256K + 8K 4K 16K ATxmega256A3U-AUR (4) 256K + 8K 4K 16K ATxmega192A3U-AU 192K + 8K 2K 16K ATxmega192A3U-AUR (4) 192K + 8K 2K 16K ATxmega128A3U-AU 128K + 8K 2K 8K ATxmega128A3U-AUR (4) 128K + 8K 2K 8K ATxmega64A3U-AU 64K + 4K 2K 4K ATxmega64A3U-AUR (4) 64K + 4K 2K 4K ATxmega256A3U-MH 256K + 8K 4K 16K ATxmega256A3U-MHR (4) 256K + 8K 4K 16K ATxmega192A3U-MH 192K + 8K 2K 16K ATxmega192A3U-MHR (4) 192K + 8K 2K 16K ATxmega128A3U-MH 128K + 8K 2K 8K ATxmega128A3U-MHR (4) 128K + 8K 2K 8K ATxmega64A3U-MH 64K + 4K 2K 4K ATxmega64A3U-MHR (4) 64K + 4K 2K 4K 32 1.6 - 3.6V Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For packaging information, see ”Packaging information” on page 68. 4. Tape and Reel. 64A 64M2 -40°C - 85°C Package Type 64A 64M2 64-lead, 14 x 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP) 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, 7.65mm exposed pad, quad flat no-lead package (QFN) 8386B–AVR–12/11 2
XMEGA A3U 2. Pinout/Block Diagram Figure 2-1. Block diagram and pinout. Power Programming, debug, test Ground External clock / Crystal pins Digital function General Purpose I /O Analog function / Oscillators 64 PA2 PA1 PA0 AVCC GND PR1 PR0 RESET/PDI PDI 63 PF7 PF6 VCC GND PF5 PF4 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PF3 Port R PA3 1 XOSC 48 PF2 PA4 2 DATA BUS 47 PF1 PA5 PA6 PA7 PB0 3 4 5 6 Port A AREF ADC AC0:1 OSC/CLK Control Sleep Controller Event System Controller Internal oscillators Real Time Counter Crypto / CRC Watchdog oscillator Watchdog Timer OCD Power Supervision Reset Controller Prog/Debug Interface 46 45 44 43 PF0 VCC GND PE7 PB1 PB2 PB3 PB4 7 8 9 10 Port B AREF ADC DAC AC0:1 Interrupt Controller Internal references CPU DMA Controller BUS matrix 42 41 40 39 PE6 PE5 PE4 PE3 PB5 11 JTAG FLASH EEPROM SRAM 38 PE2 PB6 12 DATA BUS 37 PE1 PB7 13 EVENT ROUTING NETWORK 36 PE0 GND VCC PC0 14 15 16 IRCOM TC0:1 USART0:1 SPI TWI TC0:1 USART0:1 SPI USB TC0:1 USART0:1 SPI 35 34 33 VCC GND PD7 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND VCC PD0 PD1 PD2 PD3 PD4 PD5 PD6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TWI TOSC TC0:1 USART0 Port C Port D Port E Port F Note: 1. For full details on pinout and alternate pin functions refer to ”Pinout and Pin Functions” on page 57. 3 8386B–AVR–12/11
Page 1: Features • High-performance, low-
Page 5 and 6: XMEGA A3U 3.1 Block Diagram All Atm
Page 7 and 8: XMEGA A3U 6. AVR CPU 6.1 Features
Page 9 and 10: XMEGA A3U 6.4.1 Hardware Multiplier
Page 11 and 12: XMEGA A3U 7. Memories 7.1 Features
Page 13 and 14: XMEGA A3U 7.3.4 Production Signatur
Page 15 and 16: XMEGA A3U The I/O memory address fo
Page 17 and 18: XMEGA A3U 8. DMAC - Direct Memory A
Page 19 and 20: XMEGA A3U Figure 9-1. Event system
Page 21 and 22: XMEGA A3U Figure 10-1. The clock sy
Page 23 and 24: XMEGA A3U 11. Power Management and
Page 25 and 26: XMEGA A3U 12. System Control and Re
Page 27 and 28: XMEGA A3U 13. WDT - Watchdog Timer
Page 29 and 30: XMEGA A3U Table 14-1. Reset and int
Page 31 and 32: XMEGA A3U 15.3 Output Driver All po
Page 33 and 34: XMEGA A3U 15.4 Input sensing Input
Page 35 and 36: XMEGA A3U A timer/counter can be cl
Page 37 and 38: XMEGA A3U 18. AWeX - Advanced Wavef
Page 39 and 40: XMEGA A3U 20. RTC - 16-bit Real-Tim
Page 41 and 42: XMEGA A3U the configuration of thes
Page 43 and 44: XMEGA A3U It is possible to disable
Page 45 and 46: XMEGA A3U 24. USART 24.1 Features
Page 47 and 48: XMEGA A3U 25. IRCOM - IR Communicat
Page 49 and 50: XMEGA A3U 27. CRC - Cyclic Redundan
Page 51 and 52: XMEGA A3U Both internal and externa
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XMEGA A3U The DAC has high drive st
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XMEGA A3U Figure 30-1. Analog compa
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XMEGA A3U 32. Pinout and Pin Functi
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XMEGA A3U 32.2 Alternate Pin Functi
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XMEGA A3U Table 32-6. Port F - alte
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XMEGA A3U Base address Name Descrip
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XMEGA A3U Mnemonics Operands Descri
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XMEGA A3U Mnemonics Operands Descri
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XMEGA A3U 35.2 64M2 D Marked Pin# 1
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XMEGA A3U Table 36-3. Operating vol
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XMEGA A3U Table 36-5. Current consu
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XMEGA A3U 36.5 I/O Pin Characterist
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XMEGA A3U Table 36-10. Accuracy cha
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XMEGA A3U Table 36-14. Gain error A
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XMEGA A3U 36.13 Flash and EEPROM Me
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XMEGA A3U 36.14.6 External clock ch
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XMEGA A3U 36.14.7 External 16MHz cr
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XMEGA A3U 36.14.8 External 32.768kH
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XMEGA A3U Table 36-31. SPI timing c
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XMEGA A3U Table 36-32. t HD;STA t L
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XMEGA A3U Figure 37-3. Active mode
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XMEGA A3U Figure 37-7. Active mode
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XMEGA A3U Figure 37-11. Idle mode s
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XMEGA A3U 37.1.3 Power-down mode su
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XMEGA A3U Figure 37-19. Standby sup
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XMEGA A3U 37.2.2 Output Voltage vs.
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XMEGA A3U Figure 37-27. I/O pin out
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XMEGA A3U 37.2.3 Thresholds and Hys
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XMEGA A3U 37.3 ADC Characteristics
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XMEGA A3U Figure 37-39. DNL error v
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XMEGA A3U Figure 37-43. Offset erro
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XMEGA A3U Figure 37-47. Noise vs. V
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XMEGA A3U 37.5 Analog Comparator Ch
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XMEGA A3U Figure 37-55. Analog comp
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XMEGA A3U 37.7 BOD Characteristics
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XMEGA A3U Figure 37-63. Reset pin p
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XMEGA A3U 37.9 Power-on Reset Chara
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XMEGA A3U Figure 37-70. 32.768kHz i
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XMEGA A3U 37.10.4 32MHz Internal Os
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XMEGA A3U 37.10.5 32MHz internal os
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XMEGA A3U Figure 37-82. SDA hold ti
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XMEGA A3U 39. Datasheet Revision Hi
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8.1 Features ......................
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27.1 Features .....................
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Atmel Corporation 2325 Orchard Park
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