xmega a3u - Elfa
xmega a3u - Elfa
xmega a3u - Elfa
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XMEGA A3U<br />
Figure 9-1.<br />
Event system overview and connected peripherals.<br />
CPU /<br />
Software<br />
DMA<br />
Controller<br />
ADC<br />
AC<br />
DAC<br />
Event Routing Network<br />
Event<br />
System<br />
Controller<br />
clk PER<br />
Prescaler<br />
Real Time<br />
Counter<br />
Timer /<br />
Counters<br />
USB<br />
Port pins<br />
IRCOM<br />
The event routing network consists of eight software-configurable multiplexers that control how<br />
events are routed and used. These are called event channels, and allow for up to eight parallel<br />
event routing configurations. The maximum routing latency is two peripheral clock cycles. The<br />
event system works in both active mode and idle sleep mode.<br />
8386B–AVR–12/11<br />
19
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