xmega a3u - Elfa

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XMEGA A3U 38. Errata 38.1 ATxmega64A3U, ATxmega128A3U, ATxmega192A3U, ATxmega256A3U 38.1.1 Rev. G 38.1.2 Rev. A-F • AWeX fault protection restore is not done correct in Pattern Generation Mode 1. AWeX fault protection restore is not done correctly in Pattern Generation Mode When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode (CWCM), this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation Mode (PGM), OUTOVEN should instead have been restored according to the DTILSBUF register. Problem fix/Workaround For CWCM no workaround is required. For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correct OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable the correct outputs again. For PGM in cycle-by-cycle mode there is no workaround. Not sampled. 8386B–AVR–12/11 134
XMEGA A3U 39. Datasheet Revision History 39.1 8386B – 12/11 Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 39.2 8386A – 07/11 1. Updated the Figure 2-1 on page 3. JTAG written in the white color. 2. Updated ”Overview” on page 11. 3. Updated Figure 30-1 on page 55. 4. Updated ”Instruction Set Summary” on page 64. 5. Updated ”Electrical Characteristics” on page 70. 6. Updated ”Typical Characteristics” on page 92. 7. Several changes in “Typical Characteristics” 1. Initial revision. 8386B–AVR–12/11 135
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Features • High-performance, low-
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XMEGA A3U 2. Pinout/Block Diagram F
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XMEGA A3U 3.1 Block Diagram All Atm
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XMEGA A3U 6. AVR CPU 6.1 Features
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XMEGA A3U 6.4.1 Hardware Multiplier
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XMEGA A3U 7. Memories 7.1 Features
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XMEGA A3U 7.3.4 Production Signatur
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XMEGA A3U The I/O memory address fo
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XMEGA A3U 8. DMAC - Direct Memory A
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XMEGA A3U Figure 9-1. Event system
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XMEGA A3U Figure 10-1. The clock sy
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XMEGA A3U 11. Power Management and
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XMEGA A3U 12. System Control and Re
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XMEGA A3U 13. WDT - Watchdog Timer
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XMEGA A3U Table 14-1. Reset and int
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XMEGA A3U 15.3 Output Driver All po
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XMEGA A3U 15.4 Input sensing Input
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XMEGA A3U A timer/counter can be cl
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XMEGA A3U 18. AWeX - Advanced Wavef
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XMEGA A3U 20. RTC - 16-bit Real-Tim
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XMEGA A3U the configuration of thes
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XMEGA A3U It is possible to disable
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XMEGA A3U 24. USART 24.1 Features
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XMEGA A3U 25. IRCOM - IR Communicat
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XMEGA A3U 27. CRC - Cyclic Redundan
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XMEGA A3U Both internal and externa
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XMEGA A3U The DAC has high drive st
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XMEGA A3U Figure 30-1. Analog compa
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XMEGA A3U 32. Pinout and Pin Functi
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XMEGA A3U 32.2 Alternate Pin Functi
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XMEGA A3U Table 32-6. Port F - alte
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XMEGA A3U Base address Name Descrip
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XMEGA A3U Mnemonics Operands Descri
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XMEGA A3U Mnemonics Operands Descri
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XMEGA A3U 35.2 64M2 D Marked Pin# 1
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XMEGA A3U Table 36-3. Operating vol
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XMEGA A3U Table 36-5. Current consu
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XMEGA A3U 36.5 I/O Pin Characterist
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XMEGA A3U Table 36-10. Accuracy cha
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XMEGA A3U Table 36-14. Gain error A
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XMEGA A3U 36.13 Flash and EEPROM Me
Page 83 and 84: XMEGA A3U 36.14.6 External clock ch
Page 85 and 86: XMEGA A3U 36.14.7 External 16MHz cr
Page 87 and 88: XMEGA A3U 36.14.8 External 32.768kH
Page 89 and 90: XMEGA A3U Table 36-31. SPI timing c
Page 91 and 92: XMEGA A3U Table 36-32. t HD;STA t L
Page 93 and 94: XMEGA A3U Figure 37-3. Active mode
Page 95 and 96: XMEGA A3U Figure 37-7. Active mode
Page 97 and 98: XMEGA A3U Figure 37-11. Idle mode s
Page 99 and 100: XMEGA A3U 37.1.3 Power-down mode su
Page 101 and 102: XMEGA A3U Figure 37-19. Standby sup
Page 103 and 104: XMEGA A3U 37.2.2 Output Voltage vs.
Page 105 and 106: XMEGA A3U Figure 37-27. I/O pin out
Page 107 and 108: XMEGA A3U 37.2.3 Thresholds and Hys
Page 109 and 110: XMEGA A3U 37.3 ADC Characteristics
Page 111 and 112: XMEGA A3U Figure 37-39. DNL error v
Page 113 and 114: XMEGA A3U Figure 37-43. Offset erro
Page 115 and 116: XMEGA A3U Figure 37-47. Noise vs. V
Page 117 and 118: XMEGA A3U 37.5 Analog Comparator Ch
Page 119 and 120: XMEGA A3U Figure 37-55. Analog comp
Page 121 and 122: XMEGA A3U 37.7 BOD Characteristics
Page 123 and 124: XMEGA A3U Figure 37-63. Reset pin p
Page 125 and 126: XMEGA A3U 37.9 Power-on Reset Chara
Page 127 and 128: XMEGA A3U Figure 37-70. 32.768kHz i
Page 129 and 130: XMEGA A3U 37.10.4 32MHz Internal Os
Page 131 and 132: XMEGA A3U 37.10.5 32MHz internal os
Page 133: XMEGA A3U Figure 37-82. SDA hold ti
Page 137 and 138: 8.1 Features ......................
Page 139 and 140: 27.1 Features .....................
Page 141: Atmel Corporation 2325 Orchard Park
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