1 Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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8 Improvement Trends for VLSI SoCs Enabled by Geometrical and Equivalent Scaling TRENDS 1. Higher Integration level -> exponentially increased number of components/transistors per chip. 2. Performance Scaling -> combination of Geometrical and Equivalent Scaling. 3. System implementation -> SoC + increased use of SiP 4. Higher Speed -> CPU clock rate at multiple GHz. 5. Increased Compactness -> Smaller and lighter weight electronic products 6. Lower Power -> Increased laptop, cell phone and PDA battery life. 7. Lower Cost -> Decreasing cost per function. Kenneth R. Laker, University of Pennsylvania, updated 15Jan09
9 DPE -> Digital Processing Engine From http://www.itrs.net/Links/2006Update/FinalToPost/01_SysDrivers_2006UPDATE.pdf Since digital functions will be implemented and realized mainly by software and high processing power is required, high performance consumer stationary SOCs will have many data processing engines ( DPEs). Kenneth R. Laker, University of Pennsylvania, updated 15Jan09
Page 1 and 2: Kenneth R. Laker, University of Pen
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Page 5 and 6: “ Moore's Law” Impact on Micro-
Page 7: Moore's Law and More 7 Kenneth R. L
Page 11 and 12: 11 Digital CMOS Basics Kenneth R. L
Page 13 and 14: 13 Kenneth R. Laker, University of
Page 15 and 16: Ideal nMOS and pMOS Characteristics
Page 17 and 18: Ideal CMOS Inverter 17 Inverter Tru
Page 19 and 20: Two-Input CMOS NOR Gate 19 DeMorgan
Page 21 and 22: 21 F = A⋅BC⋅D Combing the N-Hal
Page 23 and 24: 23 Some VLSI Fundamentals Kenneth R
Page 25 and 26: Typical Digital VLSI Design Abstrac
Page 27 and 28: 27 Goal of All VLSI Design Enterpri
Page 29 and 30: VLSI Design Cycle 29 Kenneth R. Lak
Page 31 and 32: Bit-Sliced Data Path Control Bit N
Page 33 and 34: 32 A B Two-Input Exclusive OR Gate
Page 35 and 36: Show SUMOUT=A⋅B⋅C ABC ⋅CARRY
Page 37 and 38: Initial Layout of One-Bit Full Adde
Page 39: Simulated Performance of One-Bit Fu

1 Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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