1 Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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30 Illustrative Circuit Design Example Design a One-Bit Adder Circuit using 0.8 ! 8µ m twin-well CMOS Technology. technology. The design specifications are: 1. Propagation Delay Times of SUM and CARRY_Out signals: ≤ 1.2 ns 2. Rise and Fall Times of SUM and CARRY_Out signals: ≤ 1.2 ns 3. Circuit Die Area: ≤ 1500 m 2 4. Dynamic Power Dissipation (@ V DD = 5 V and f max = 20 MHz): ≤ 1 mW Kenneth R. Laker, University of Pennsylvania, updated 15Jan09
Bit-Sliced Data Path Control Bit N Data IN Register ADDER Shifter Multiplier Data OUT Bit 0 Kenneth R. Laker, University of Pennsylvania, updated 15Jan09
Page 1 and 2: Kenneth R. Laker, University of Pen
Page 3 and 4: Kenneth R. Laker, University of Pen
Page 5 and 6: “ Moore's Law” Impact on Micro-
Page 7 and 8: Moore's Law and More 7 Kenneth R. L
Page 9 and 10: 9 DPE -> Digital Processing Engine
Page 11 and 12: 11 Digital CMOS Basics Kenneth R. L
Page 13 and 14: 13 Kenneth R. Laker, University of
Page 15 and 16: Ideal nMOS and pMOS Characteristics
Page 17 and 18: Ideal CMOS Inverter 17 Inverter Tru
Page 19 and 20: Two-Input CMOS NOR Gate 19 DeMorgan
Page 21 and 22: 21 F = A⋅BC⋅D Combing the N-Hal
Page 23 and 24: 23 Some VLSI Fundamentals Kenneth R
Page 25 and 26: Typical Digital VLSI Design Abstrac
Page 27 and 28: 27 Goal of All VLSI Design Enterpri
Page 29: VLSI Design Cycle 29 Kenneth R. Lak
Page 33 and 34: 32 A B Two-Input Exclusive OR Gate
Page 35 and 36: Show SUMOUT=A⋅B⋅C ABC ⋅CARRY
Page 37 and 38: Initial Layout of One-Bit Full Adde
Page 39: Simulated Performance of One-Bit Fu

1 Kenneth R. Laker, University of Pennsylvania, updated 15Jan09

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