Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 1

Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 1

Three Domain View of VLSI Design Flow at One Level
FUNCTIONAL DESIGN
Verilog
Verilog/Spectre
Verilog/Cadence
Extract Parasitic Elements
Spectre SPICE
(Spectre)
1. Design Rule Check (DRC)
2. Layout Versus Schematic
(LVS) Check
3. Post layout simulation (PLS)
Cadence
(Virtuoso)
PLS
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 2

Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 3

Metrics By Which Design Success is Measured:
metrics.
(and near neighbor boundaries)
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 4

Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 5

carry
carry
carry
carry
Hierarchical & Modular 4-bit Adder
add
add4
add add add
b[3:0]
a[3:0]
b
a
+
+
+
+
c0
co3
c
+
s[3:0]
s
co
sum
sum
sum
sum
c
b
a
c
sum s
a b carry
co
nand
nor
nand
nor
nand
nor
nand
inv inv inv inv
nor
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 6

[3:0]
a[3:0]
c0
+
add4 +
+
+
co3
Hierarchical & Modular Layout
s[3:0]
b[3]
a[3]
b[2]
a[2]
b[1]
a[1]
b[0]
a[0]
(0,0)
add4 Layout
c0
add[3]
add[2]
add[1]
add[0]
co3
(100,400)
s[3]
(100,300)
s[2]
(100,200)
s[1]
(100,100)
s[1]
(0,100)
(0,75)
(0,25)
(0,0)
add Cell
b[i]
(50,100)
c[i]
add[i]
a[i]
co[i]
(50,0)
s[i]
7
(100,100)
(100,50)
(100,0)
Kenneth R. Laker, University of Pennsylvania, updated 12Apr11
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 7

8
Unused die area ->
inefficient layout
Structural Hierarchy
1 mapped poorly into
Physical Hierarchy.
Better
mapping!
Miss-mappings between Structural and Physical Hierarchies usually avoided by using
automatic layout system.
Kenneth R. Laker, University of Pennsylvania, updated 12Apr11
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 8

REGULARITY
DESIGN THE CHIP REUSING AS MANY IDENTICAL MODULES,
CIRCUITS, DEVICES AS POSSIBLE. REGULARITY CAN EXIST
AT ALL LEVELS OF THE DESIGN HIERARCHY.
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 9

LOCALITY (PHYSICAL)
TIME LOCALITY: modules are synchronized by common clock.
-> Critical timing paths are kept within module boundaries or within near neighbor
Boundaries.
-> Place modules to minimize large or “global” inter-module signal routes.
-> Care take to realize robust clock generation and distribution.
-> Signal routes between modules with large physical separation need sufficient
time to traverse route.
-> Replicate modules, if necessary, to alleviate delay issues caused by long intermodule
signal routes.
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 10

Time-to-Market and
Design Investment
Increasing (for a given
application)
Performance Increasing,
Die Are Decreasing,
Power Dissipation
Decreasing (for a given
application)
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 11

are
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 12

Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 13

Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 14

Basic FPGA Architecture
I/O Modules Clock Buffer
(Configurable Logic Blocks - CLBs)
Logic Modules
Segmented Routing Tracks
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 15

State-of-the-Art FPGA Architecture
Programmable
Function Unit
(PFU) – perform
logic, arithmetic,
Distributed RAM
& ROM functions.
Flexible Sys I/O
Buffers – support
LVCMOS, LVDS,
etc.
Sys Clock – PLLs
& DLLs for clock
management.
Embedded 3.125 Gbps
SERDES – support PCI
express, Ethernet.
Sys DSP Blocks –
implement
multipliers,
adders,
subtractors,
accumulators.
Configuration Port
– supports SPI,
serial and parallel
configuration.
http://www.latticesemi.com/products/fpga/ecp2/optimizedfpgaarchitecture.cfm
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 16

Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 17

Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 18

IMPORTANT PACKAGE DESIGN CONCERNS:
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 19

Package Bonding Techniques
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 20

Summary of Package Types
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 21

A System-In-Package Solution
High density memory chip
chip
http://www.ansoft.com/leadinginsight/pdf/System%20in%20Package.pdf, slide 15
Kenneth R. Laker, University of Pennsylvania, updated 04Apr12 22