AGFA d-lab.3 Digital Compact Lab

Repair
Printer
FPGA
FPGA (Field Programmable Gate Array ): After the
supply voltage has been applied, its function must
be loaded which is done by the Microcontroller (µC),
allowing Updates in the field.
The FPGA represents the central processing unit for
the data pipeline in which the process control, the
pixel processing, error corrections, service modes,
the communication with the µC are implemented.
Communication of the Microcontroller with the
modules is via a
13-bit wide internal data bus. Address, data and
control signals from the µC are latched with the
master clock (60,9 MHz).
FPGA Module:
1. Address decoder
It decodes the synchronised controller addresses
and generates select signals for the individual
modules.
2. Address generator
It minimises the signal lines to the µC (7 instead
of 18 address lines). When a certain field is
addressed, the generator is active. The
addresses for the external LUT red, green, blue
and the internal RAM and ROM are formed. The
µC has only one address for each memory bank.
To address the memory cells of a number n of a
bank, the µC must call the bank address n times,
e.g. 2 18 times when reading or writing an LUT
page of a colour. The address is incremented by
1 at every computer access. The internal address
counter must be cleared by a command prior to
every new memory bank access.
3. Image detector
It stores the 8 low order Bits of the first pixel of
each image in an internal register which can be
read by the µC during the time until the next
image is output and which holds an image
number between 1 and 99.
AGFA d-lab.3 2001-01-02 /PN 9009 6.3.17