AGFA d-lab.3 Digital Compact Lab

Printer
Repair
Functional Description, Image Processing
General Task
This part of the printed circuit has the task to
transfer the serial image data stream coming from
the image processing to three parallel data pipelines
(RGB), include various correction mechanisms in
the calculation and make available three analogue
signals whose amplitude and timing are adjusted to
the output medium of the print engine. The
description below follows the signal stream.
LVDS Interface
The image data coming from the image processing
unit is transmitted to the Printer Mainboard via the
LVDS interface by serial transmission.
1. The LVDS Channel Link Receiver DS 90CR284
can receive serial data on 5 line pairs (4 data +
1 clock pair) and convert it to a 28-bit parallel
data word. Four line pairs on the Printer
Mainboard (3 data + 1 clock pair) are used for
the serial transmission and converted to an
18-bit data word (16 Bit pixel data + 2 Bit control
data for the Low and High part). A pixel date
(32 Bit) is composed of two time-multiplex
transmitted 16-bit data words (Low + High part).
The serial clock frequency is 40 Mhz.
2. The differential driver sends the FIFO status
(FAF) via the LVDS interface.
Sync FIFO
The data paralleled by the Channel Link Receiver is
entered in a FIFO. The FIFO is used to buffer and
synchronise the image data for the subsequent
image processing units. It is read with the pixel
clock under Pipeline control. The FIFO consists of
four circuits (each one organised 4096 x 9 Bit) which
are circuited to 4096 x 32 Bit.
For an image width of 8,5 inch, 1,2 pixel lines can
be buffered so that the Retrace time can be used for
the data transfer – reduction of the data rate.
6.3.16 2001-01-02 /PN 9009 AGFA d-lab.3