AGFA d-lab.3 Digital Compact Lab
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AGFA d-lab.3 Digital Compact Lab

AGFA d-lab.3 Digital Compact Lab AGFA d-lab.3 Digital Compact Lab

saal.group.com
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Repair Printer PF_GS01 – Printer Mainboard Functional Description, general PF_GS01 (8.8060.2000) Functions: 1. Image data processing 2. Printer control In detail: − Transformation of the serial image data stream (input) to the 3 parallel currents RGB: serial clock 40 MHz − Data buffering in the FIFO: 1,2 pixel lines for an image width of 8,5 Inch − Facet correction for each one of the 18 facets for RGB: < 1% − Correction Laser noise: ± 4% − Correction Laser drift − LUT calculation − Pixel delay: up to 16 pixels − Pixel shift in 1/8 pixel steps − Definition of the line beginning by means of the register value − Pixel register for text exposures − LUT calculation: Adjustment of the densityproportional image data to the sensitivity of the paper, taking into account the transfer characteristics of AOM, Polygon, corrections dlabr135 AGFA d-lab.3 2001-01-02 /PN 9009 6.3.15

Printer Repair Functional Description, Image Processing General Task This part of the printed circuit has the task to transfer the serial image data stream coming from the image processing to three parallel data pipelines (RGB), include various correction mechanisms in the calculation and make available three analogue signals whose amplitude and timing are adjusted to the output medium of the print engine. The description below follows the signal stream. LVDS Interface The image data coming from the image processing unit is transmitted to the Printer Mainboard via the LVDS interface by serial transmission. 1. The LVDS Channel Link Receiver DS 90CR284 can receive serial data on 5 line pairs (4 data + 1 clock pair) and convert it to a 28-bit parallel data word. Four line pairs on the Printer Mainboard (3 data + 1 clock pair) are used for the serial transmission and converted to an 18-bit data word (16 Bit pixel data + 2 Bit control data for the Low and High part). A pixel date (32 Bit) is composed of two time-multiplex transmitted 16-bit data words (Low + High part). The serial clock frequency is 40 Mhz. 2. The differential driver sends the FIFO status (FAF) via the LVDS interface. Sync FIFO The data paralleled by the Channel Link Receiver is entered in a FIFO. The FIFO is used to buffer and synchronise the image data for the subsequent image processing units. It is read with the pixel clock under Pipeline control. The FIFO consists of four circuits (each one organised 4096 x 9 Bit) which are circuited to 4096 x 32 Bit. For an image width of 8,5 inch, 1,2 pixel lines can be buffered so that the Retrace time can be used for the data transfer – reduction of the data rate. 6.3.16 2001-01-02 /PN 9009 AGFA d-lab.3

Repair<br />

Printer<br />

PF_GS01 – Printer Mainboard<br />

Functional Description, general<br />

PF_GS01 (8.8060.2000)<br />

Functions:<br />

1. Image data processing<br />

2. Printer control<br />

In detail:<br />

− Transformation of the serial image data stream<br />

(input) to the 3 parallel currents RGB: serial clock<br />

40 MHz<br />

− Data buffering in the FIFO:<br />

1,2 pixel lines for an image width of 8,5 Inch<br />

− Facet correction for each one of the 18 facets for<br />

RGB: < 1%<br />

− Correction Laser noise: ± 4%<br />

− Correction Laser drift<br />

− LUT calculation<br />

− Pixel delay: up to 16 pixels<br />

− Pixel shift in 1/8 pixel steps<br />

− Definition of the line beginning by means of the<br />

register value<br />

− Pixel register for text exposures<br />

− LUT calculation: Adjustment of the densityproportional<br />

image data to the sensitivity of the<br />

paper, taking into account the transfer<br />

characteristics of AOM, Polygon, corrections<br />

dlabr135<br />

<strong>AGFA</strong> d-<strong>lab.3</strong> 2001-01-02 /PN 9009 6.3.15

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