AGFA d-lab.3 Digital Compact Lab

Repair
Printer
ST29 Logic Source voltage
1 +6,5V
2 +6,5V
3 +6,5V
4 GND (digital GND)
5 GND (digital GND)
6 GND (digital GND)
ST30 FPGA Boundary Scan Operation: n.c
1 BSCAN-TDI Test Data Input
2 BSCAN-TCK Test Clock
3 BSCAN-TMS Test Mode Select
4 BSCAN-TDO Test Data Output
5 /INITX Bi-directional signal, low during the stabilisation of the
operating voltage and clearing of the configuration
memory as Input held low FPGA in wait state prior to
the configuration start
6 n.c.
ST32 FPGA Down Load Operation: n.c
1 +5V
2 GND
3 CCLK Clock input
4 DONE bi-directional signal, as Output shows the status of the
initialisation, as Input delays the global Logic reset and
the Output enable
5 DIN Data input
6 /PROG initialises the configuration process
7 /INITX bi-directional signal, low during the stabilisation of the
operating voltage and clearing of the configuration
memory as Input held low FPGA in wait state prior to
the configuration start
8 RSTX Reset FPGA logic
ST 33
ST 34
Test point for EOL signal
Test point for Picture work
ST 35 Read back FPGA Operation: n.c.
1 GND
2 TRIG Trigger
3 RBT Read back trigger
4 RBD Read back date
XS 1 Screen LVDS cable Operation: n.c
XS 2
Screen cable LFB distributor
AGFA d-lab.3 2001-01-02 /PN 9009 6.2.21