Preliminary - Reptips

DIGITAL BLOCK DIAGRAM
0
2
DIGITAL
VIDEO IF
DDR RAM
TO
JUNCTION
(VIDEO)
CN7108
CN1002
AO_IEC958, AI_D[0], A_MUTE2[H], K_BUS_CLK
K_BUS_REQ, SYS_RESET[L], K_BUS_IN/OUT
SW5V, SW12V, D5V, D3.3V
D2.5V, D1.8V, V3.3V
SDRAM_DQ[0-15]
RA1609
to
RA1612
DDR_DQ[0-15]
IC1601
IC1603
DDR SDRAM
SDRAM_DQ[16-31]
RA1613
to
RA1616
DDR_DQ[16-31]
IC1602
IC1604
DDR SDRAM
AO_SCLK, AO_MCLKO, AO_FSYNC, DAC_RST[L]
DAC_SCL, DAC_SDA, AO_D[0], A_DAC_CS
DDR_A[0-12]
TO
JUNCTION
(VIDEO)
CN7109
CN1001
CIN
VYIN
YV_OUT
C_OUT
CB_OUT
CR_OUT
Y
C
Cb
Cr
Y
C
Q1008
SW
Y
Q1002 to Q1005
BUF
IC1001
Video
Controller
IC1002
SDRAM
VI_D[2-9], VIDEO_RST[L]
VO_D[0-15], SPI_MOSI
VIDEO_27M, VIDEO_CS
VIDEO_MUTE[H], SPI_CLK
VIDEO_RXD
AP, A0 to A9,DQ0 to DQ15
UDQM, WE,CAS, RAS
VI_D[2-9]
VO_D[0-15]
VIDEO_27M
SDRAM_A[0-12]
SDRAM_A[14-17]
SDRAM_CKE
SDRAM_RAS_L
SDRAM_CAS_L
SDRAM_WE_L
RA1625
to
RA1628
R1601
to
R1604
DDR_BA[0]
DDR_BA[1]
DDR_CS[0]
DDR_CKE
DDR_RAS_L
DDR_CAS_L
DDR_WE_L
SDRAM_CLK[0]
DDR_CLK[0]
TO
JUNCTION
(VIDEO)
CN7105
OPEN
CN1404
CN1403
MEDIA PROCESSOR
JLIP_TX
JLIP_RX
UART2_TX
UART2_RX
VI_D[2-9], VO_D[0-15]
SDRAM_DQ[0- 31]
SDRAM_A[0-12]
SDRAM_A[14-17]
SDRAM_DQS[0] to [3]
SDRAM_DQM[0] to [3]
SDRAM_CLK[0], SDRAM_CLK[1]
SDRAM_CLK_L[0], SDRAM_CLK_L[1]
SDRAM_CKE, SDRAM_RAS_L
SDRAM_CLK[1]
SDRAM_CLK_L[0]
SDRAM_CLK_L[1]
SDRAM_DQM[0] to [3]
SDRAM_DQS[0] to [3]
R1613
to
R1616
RA1653
to
R1660
DDR_CLK[1]
DDR_CLK_L[0]
DDR_CLK_L[1]
DDR_DQM[2],[3]
DDR_DQS[2],[3]
DDR_DQM[0],[1]
DDR_DQS[0],[1]
SDRAM_CAS_L, SDRAM_WE_L
1394
J4112
3 6
JACK
CN4104
CN1801
1394PFY
TPA+
TPA-
TPB+
TPB-
IC1801
IEEE1394
Controller
PHY_RESET[L]
PHY_LREQ
PHY_CLK
PHY_CNA
PHY_CTL[0]
PHY_CTL[1]
PHY_DATA[0-7]
PHY_LPS
PHY_LINK_ON
IC1401
Media
Processor
VIDEO_RXD, VIDEO_CS
VIDEO_27M, AO_SCLK, AO_FSYNC
AO_MCLKO, AO_IEC958, AO_D[0]
AI_D[0], SPI_MOSI, SPI_CLK
DAC_SCL, DAC_SDA, A_DAC_CS
DAC_RST[L], VIDEO_RST[L], VIDEO_MUTE[H]
IC1404
3.3V --> 5.0V
A_MUTE2[H]
K_BUS_CLK
K_BUS_REQ
ATAPI IF
FOR JIG
CN1404
FLASH
IC1201
Flash
memory
IC1203
IC1204
Transparent
MADD[1-5]
MADD[6-22]
E5_RESET[L]
LH_AR[6] to LH_AR[21]
MADD[6-21]
ALE
MADD[1-5]
MADD[6-22]
E5_RESET[L]
UART2_TX, UART2_RX
RD/WR[L]
OE[L]/LDS[L]
CS[0]
MADD[1-5]
RD/WR[L]
OE[L]/LDS[L]
CS[0]
MADD[1-5]
ALE
IC1405
5.0V --> 3.3V
ATA_RESET, ATA_DAT[0-15], ATA_DMARQ
ATA_IORDY, ATA_INTRQ, ATA_DIOW[L]
ATA_DIOR[L], ATA_DMAACK[L], ATA_ADD[0] to [4]
SYS_RESET[L]
K_BUS_IN/OUT
ATA_RESET
ATA_DAT[0-15]
ATA_DIOW[L]
ATA_DIOR[L]
ATA_DMAACK[L]
ATA_ADD[0] to [4]
ATA_DMARQ
ATA_IORDY
ATA_INTRQ
RA2201
to
RA2205
RA2206
RA2207
HD_AT[0] to [15]
RSTATA
DMARQ, DIOW, DIOR
IORDY, DMACK, INT_ATA
ATA_A0, ATA_1,ATA_A2
CS1FX, CS3FX
CN2201
TO
DVD
Recorder
Unit
2-63 2-64