3GPP TS 36.212, "Multiplexing and channel coding"
3GPP TS 36.212, "Multiplexing and channel coding"
3GPP TS 36.212, "Multiplexing and channel coding"
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Release 8<br />
13<br />
<strong>3GPP</strong> <strong>TS</strong> <strong>36.212</strong> V8.1.0 (2007-11)<br />
x k<br />
z k<br />
c k<br />
z′<br />
k<br />
c′<br />
k<br />
x′<br />
k<br />
Figure 5.1.3-2: Structure of rate 1/3 turbo encoder (dotted lines apply for trellis termination only)<br />
5.1.3.2.2 Trellis termination for turbo encoder<br />
Trellis termination is performed by taking the tail bits from the shift register feedback after all information bits are<br />
encoded. Tail bits are padded after the encoding of information bits.<br />
The first three tail bits shall be used to terminate the first constituent encoder (upper switch of figure 5.1.3-2 in lower<br />
position) while the second constituent encoder is disabled. The last three tail bits shall be used to terminate the second<br />
constituent encoder (lower switch of figure 5.1.3-2 in lower position) while the first constituent encoder is disabled.<br />
The transmitted bits for trellis termination shall then be:<br />
(0)<br />
d<br />
K<br />
= x K<br />
(1)<br />
d<br />
K<br />
= z K<br />
(2)<br />
K<br />
= x K + 1<br />
(0)<br />
,<br />
K + 1 = z K + 1<br />
d , d = x′<br />
K<br />
(1)<br />
,<br />
K + 1 = xK<br />
+ 2<br />
d , d = z′<br />
K<br />
(2)<br />
K + 1 = K +<br />
(0)<br />
(0)<br />
K + 2<br />
, d K<br />
′<br />
+ 3<br />
= z K + 1<br />
(1)<br />
(1)<br />
K + 2<br />
, d K<br />
′<br />
+ 3<br />
= x K + 2<br />
(2)<br />
K<br />
′<br />
+ 2 +<br />
(2)<br />
K + 3<br />
′<br />
+<br />
d , d z 2 , d = x K 1 , d = z K 2<br />
5.1.3.2.3 Turbo code internal interleaver<br />
The bits input to the turbo code internal interleaver are denoted by c 0 , c1,...,<br />
c K −1<br />
, where K is the number of input bits.<br />
The bits output from the turbo code internal interleaver are denoted by c 0<br />
′ , c1′<br />
,..., c′<br />
K −1<br />
.<br />
The relationship between the input <strong>and</strong> output bits is as follows:<br />
ci′ = cΠ()<br />
i , i=0, 1,…, (K-1)<br />
<strong>3GPP</strong>