dsPIC30F2010 Data Sheet - Microchip

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dsPIC30F2010 TABLE 4-2: TABLE 4-3: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 Note 1: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) XB Bit-Reversed Address Modifier Value (1) 32768 0x4000 16384 0x2000 8192 0x1000 4096 0x0800 2048 0x0400 1024 0x0200 512 0x0100 256 0x0080 128 0x0040 64 0x0020 32 0x0010 16 0x0008 8 0x0004 4 0x0002 2 0x0001 Modifier values greater than 256 words exceed the data memory available on the dsPIC30F2010 device. DS70118J-page 36 © 2011 Microchip Technology Inc.
dsPIC30F2010 5.0 INTERRUPTS Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157). The dsPIC30F2010 has 24 interrupt sources and four processor exceptions (traps), which must be arbitrated based on a priority scheme. The CPU is responsible for reading the Interrupt Vector Table (IVT) and transferring the address contained in the interrupt vector to the program counter. The interrupt vector is transferred from the program data bus into the program counter, via a 24-bit wide multiplexer on the input of the program counter. The Interrupt Vector Table (IVT) and Alternate Interrupt Vector Table (AIVT) are placed near the beginning of program memory (0x000004). The IVT and AIVT are shown in Figure 5-1. The interrupt controller is responsible for preprocessing the interrupts and processor exceptions, prior to their being presented to the processor core. The peripheral interrupts and traps are enabled, prioritized and controlled using centralized special function registers: • IFS0, IFS1, IFS2 All interrupt request flags are maintained in these three registers. The flags are set by their respective peripherals or external signals, and they are cleared via software. • IEC0, IEC1, IEC2 All interrupt enable control bits are maintained in these three registers. These control bits are used to individually enable interrupts from the peripherals or external signals. • IPC0... IPC11 The user-assignable priority level associated with each of these interrupts is held centrally in these twelve registers. • IPL The current CPU priority level is explicitly stored in the IPL bits. IPL is present in the CORCON register, whereas IPL are present in the STATUS Register (SR) in the processor core. • INTCON1, INTCON2 Global interrupt control functions are derived from these two registers. INTCON1 contains the control and status flags for the processor exceptions. The INTCON2 register controls the external interrupt request signal behavior and the use of the alternate vector table. Note: All interrupt sources can be user-assigned to one of seven priority levels, 1 through 7, via the IPCx registers. Each interrupt source is associated with an interrupt vector, as shown in Figure 5-1. Levels 7 and 1 represent the highest and lowest maskable priorities, respectively. Note: If the NSTDIS bit (INTCON1) is set, nesting of interrupts is prevented. Thus, if an interrupt is currently being serviced, processing of a new interrupt is prevented, even if the new interrupt is of higher priority than the one currently being serviced. Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. Assigning a priority level of 0 to an interrupt source is equivalent to disabling that interrupt. The IPL bits become read-only whenever the NSTDIS bit has been set to ‘1’. Certain interrupts have specialized control bits for features like edge or level triggered interrupts, interrupt-on-change, etc. Control of these features remains within the peripheral module which generates the interrupt. The DISI instruction can be used to disable the processing of interrupts of priorities 6 and lower for a certain number of instructions, during which the DISI bit (INTCON2) remains set. When an interrupt is serviced, the PC is loaded with the address stored in the vector location in Program Memory that corresponds to the interrupt. There are 63 different vectors within the IVT (refer to Figure 5-1). These vectors are contained in locations 0x000004 through 0x0000FE of program memory (refer to Figure 5-1). These locations contain 24-bit addresses, and in order to preserve robustness, an address error trap will take place should the PC attempt to fetch any of these words during normal execution. This prevents execution of random data as a result of accidentally decrementing a PC into vector space, accidentally mapping a data space address into vector space or the PC rolling over to 0x000000 after reaching the end of implemented program memory space. Execution of a GOTO instruction to this vector space will also generate an address error trap. © 2011 Microchip Technology Inc. DS70118J-page 37
Page 1 and 2: dsPIC30F2010 Data Sheet High-Perfor
Page 3 and 4: dsPIC30F2010 High-Performance, 16-b
Page 5 and 6: dsPIC30F2010 Pin Diagrams 28-Pin SD
Page 7 and 8: dsPIC30F2010 1.0 DEVICE OVERVIEW No
Page 9 and 10: dsPIC30F2010 Table 1-1 provides a b
Page 11 and 12: dsPIC30F2010 2.0 CPU ARCHITECTURE O
Page 13 and 14: dsPIC30F2010 FIGURE 2-1: PROGRAMMER
Page 15 and 16: dsPIC30F2010 FIGURE 2-2: DSP ENGINE
Page 17 and 18: dsPIC30F2010 The SA and SB bits are
Page 19 and 20: dsPIC30F2010 3.0 MEMORY ORGANIZATIO
Page 21 and 22: dsPIC30F2010 3.1.1 DATA ACCESS FROM
Page 23 and 24: dsPIC30F2010 FIGURE 3-5: DATA SPACE
Page 25 and 26: dsPIC30F2010 FIGURE 3-7: DATA SPACE
Page 27 and 28: dsPIC30F2010 All byte loads into an
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Page 31 and 32: dsPIC30F2010 4.0 ADDRESS GENERATOR
Page 33 and 34: dsPIC30F2010 4.2 Modulo Addressing
Page 35: dsPIC30F2010 4.2.3 MODULO ADDRESSIN
Page 39 and 40: dsPIC30F2010 5.2 Reset Sequence A R
Page 41 and 42: dsPIC30F2010 5.4 Interrupt Sequence
Page 43 and 44: dsPIC30F2010 6.0 FLASH PROGRAM MEMO
Page 45 and 46: dsPIC30F2010 6.6 Programming Operat
Page 49 and 50: dsPIC30F2010 7.0 DATA EEPROM MEMORY
Page 51 and 52: dsPIC30F2010 7.3 Writing to the Dat
Page 53 and 54: dsPIC30F2010 8.0 I/O PORTS Note: Th
Page 57 and 58: dsPIC30F2010 9.0 TIMER1 MODULE Note
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Page 61 and 62: dsPIC30F2010 10.0 TIMER2/3 MODULE N
Page 63 and 64: dsPIC30F2010 FIGURE 10-2: 16-BIT TI
Page 67 and 68: dsPIC30F2010 11.0 INPUT CAPTURE MOD
Page 69 and 70: dsPIC30F2010 11.2 Input Capture Ope
Page 71 and 72: dsPIC30F2010 12.0 OUTPUT COMPARE MO
Page 73 and 74: dsPIC30F2010 12.4.2 PWM PERIOD The
Page 75 and 76: dsPIC30F2010 13.0 QUADRATURE ENCODE
Page 77 and 78: dsPIC30F2010 13.3 Position Measurem
Page 81 and 82: dsPIC30F2010 14.0 MOTOR CONTROL PWM
Page 83 and 84: dsPIC30F2010 14.1 PWM Time Base The
Page 85 and 86: dsPIC30F2010 14.3 Edge-Aligned PWM
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dsPIC30F2010 FIGURE 14-4: DEAD-TIME
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dsPIC30F2010 14.14 PWM Special Even
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dsPIC30F2010 15.0 SPI MODULE Note:
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dsPIC30F2010 15.3 Slave Select Sync
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dsPIC30F2010 16.0 I 2 C MODULE Note
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dsPIC30F2010 16.2 I 2 C Module Addr
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dsPIC30F2010 16.8 Slope Control The
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© 2011 Microchip Technology Inc. D
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dsPIC30F2010 17.0 UNIVERSAL ASYNCHR
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dsPIC30F2010 17.2 Enabling and Sett
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dsPIC30F2010 17.5.2 FRAMING ERROR (
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dsPIC30F2010 18.0 10-BIT HIGH-SPEED
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dsPIC30F2010 18.4 Programming the S
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dsPIC30F2010 TABLE 18-1: 10-BIT A/D
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dsPIC30F2010 18.7.3.3 600 ksps Conf
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dsPIC30F2010 18.13 Configuring Anal
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dsPIC30F2010 19.0 SYSTEM INTEGRATIO
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dsPIC30F2010 FIGURE 19-1: OSCILLATO
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dsPIC30F2010 19.2.3 LP OSCILLATOR C
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dsPIC30F2010 19.3 Reset The dsPIC30
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dsPIC30F2010 19.3.1.1 POR with Long
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dsPIC30F2010 19.4 Watchdog Timer (W
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dsPIC30F2010 20.0 INSTRUCTION SET S
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dsPIC30F2010 TABLE 20-1: Wb Wd Wdo
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dsPIC30F2010 TABLE 20-2: Base Instr
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dsPIC30F2010 TABLE 20-2: Base Instr
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dsPIC30F2010 21.0 DEVELOPMENT SUPPO
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dsPIC30F2010 21.7 MPLAB SIM Softwar
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dsPIC30F2010 22.0 ELECTRICAL CHARAC
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dsPIC30F2010 TABLE 22-4: DC TEMPERA
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dsPIC30F2010 TABLE 22-6: DC CHARACT
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dsPIC30F2010 TABLE 22-8: DC CHARACT
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dsPIC30F2010 TABLE 22-10: DC CHARAC
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dsPIC30F2010 TABLE 22-13: AC CHARAC
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dsPIC30F2010 TABLE 22-16: Clock Osc
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dsPIC30F2010 FIGURE 22-5: RESET, WA
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dsPIC30F2010 FIGURE 22-7: TIMER EXT
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dsPIC30F2010 FIGURE 22-8: TIMERQ (Q
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dsPIC30F2010 FIGURE 22-11: OC/PWM M
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dsPIC30F2010 FIGURE 22-14: QEA/QEB
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dsPIC30F2010 FIGURE 22-16: SPI MODU
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dsPIC30F2010 FIGURE 22-18: SPI MODU
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dsPIC30F2010 TABLE 22-35: SPI MODUL
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dsPIC30F2010 TABLE 22-36: I 2 C BUS
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dsPIC30F2010 TABLE 22-37: I 2 C BUS
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dsPIC30F2010 TABLE 22-38: AC CHARAC
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dsPIC30F2010 FIGURE 22-25: 10-BIT H
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dsPIC30F2010 23.0 PACKAGING INFORMA
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dsPIC30F2010 © 2011 Microchip
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dsPIC30F2010 N D E1 E NOTE 1 1
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dsPIC30F2010 APPENDIX A: Revision F
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dsPIC30F2010 INDEX Numerics 10-bit
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dsPIC30F2010 Instruction Addressing
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dsPIC30F2010 TimerQ (QEI Module) Ex
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dsPIC30F2010 THE MICROCHIP WEB SITE
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dsPIC30F2010 PRODUCT IDENTIFICATION
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dsPIC30F2010 Data Sheet - Microchip

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