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<strong>STM32W108C8</strong><br />
Serial interfaces<br />
9.11.2 I 2 C control 1 register (SCx_TWICTRL1)<br />
Table 61.<br />
Address offset: 0xC84C (SC1_TWICTRL1) and 0xC04C (SC2_TWICTRL1)<br />
Reset value: 0x0000 0000<br />
I 2 C control 1 register (SCx_TWICTRL1)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
SC_T<br />
WISTO<br />
P<br />
SC_T<br />
WISTA<br />
RT<br />
SC_T<br />
WISEN<br />
D<br />
SC_T<br />
WIREC<br />
V<br />
rw rw rw rw<br />
Bit 3 SC_TWISTOP: Setting this bit sends the STOP command. It clears when the command<br />
completes.<br />
Bit 2 SC_TWISTART: Setting this bit sends the START or repeated START command. It clears when<br />
the command completes.<br />
Bit 1 SC_TWISEND: Setting this bit transmits a byte. It clears when the command completes.<br />
Bit 0 SC_TWIRECV: Setting this bit receives a byte. It clears when the command completes.<br />
9.11.3 I 2 C control 2 register (SCx_TWICTRL2)<br />
Table 62.<br />
Address offset: 0xC850 (SC1_TWICTRL2) and 0xC050 (SC2_TWICTRL2)<br />
Reset value: 0x0000 0000<br />
I 2 C control 2 register (SCx_TWICTRL2)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
SC_T<br />
WIACK<br />
rw<br />
Bit 0 SC_TWIACK: Setting this bit signals ACK after a received byte. Clearing this bit signals NACK<br />
after a received byte.<br />
Doc ID 018587 Rev 2 96/215
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