STM32W108C8

Serial interfaces
STM32W108C8
9.9.5 Serial clock exponential prescaler register (SCx_RATEEXP)
Table 59.
Address offset: 0xC864 (SC1_RATEEXP) and 0xC064 (SC2_RATEEXP)
Reset value: 0x0000 0000
Serial clock exponential prescaler register (SCx_RATEEXP)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SC_RATEEXP
rw
Bits [3:0] SC_RATEEXP: The exponential component (EXP) of the clock rate in the equation:
Rate = 12 MHz / ( (LIN + 1) * (2^EXP) )
9.10 SPI slave mode registers
Refer to Section 9.9: SPI master mode registers on page 92 for a description of the
SCx_DATA, SCx_SPICFG, and SCx_SPISTAT registers.
9.11 Inter-integrated circuit (I 2 C) interface registers
9.11.1 I 2 C status register (SCx_TWISTAT)
Table 60.
Address offset: 0xC844 (SC1_TWISTAT) and 0xC044 (SC2_TWISTAT)
Reset value: 0x0000 0000
I 2 C status register (SCx_TWISTAT)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SC_T
WICM
DFIN
SC_T
WIRXF
IN
SC_T
WITXF
IN
SC_T
WIRXN
AK
r r r r
Bit 3 SC_TWICMDFIN: This bit is set when a START or STOP command completes. It clears on the
next I2C bus activity.
Bit 2 SC_TWIRXFIN: This bit is set when a byte is received. It clears on the next I 2 C bus activity.
Bit 1 SC_TWITXFIN: This bit is set when a byte is transmitted. It clears on the next I 2 C bus activity.
Bit 0 SC_TWIRXNAK: This bit is set when a NACK is received from the slave. It clears on the next
I 2 C bus activity.
95/215 Doc ID 018587 Rev 2