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<strong>STM32W108C8</strong><br />
Serial interfaces<br />
9.9.3 SPI status register (SCx_SPISTAT)<br />
Table 57.<br />
Address offset: 0xC840 (SC1_SPISTAT) and 0xC040 (SC2_SPISTAT)<br />
Reset value: 0x0000 0000<br />
SPI status register (SCx_SPISTAT)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
SC_SPI<br />
TXIDLE<br />
SC_SPI<br />
TXFREE<br />
SC_SPI<br />
RXVAL<br />
SC_SPI<br />
RXOVF<br />
r r r r<br />
Bit 3 SC_SPITXIDLE: This bit is set when both the transmit FIFO and the transmit serializer are<br />
empty.<br />
Bit 2 SC_SPITXFREE: This bit is set when the transmit FIFO has space to accept at least one byte.<br />
Bit 1 SC_SPIRXVAL: This bit is set when the receive FIFO contains at least one byte.<br />
Bit 0 SC_SPIRXOVF: This bit is set if a byte is received when the receive FIFO is full. This bit is<br />
cleared by reading the data register.<br />
9.9.4 Serial clock linear prescaler register (SCx_RATELIN)<br />
Table 58.<br />
Address offset: 0xC860 (SC1_RATELIN) and 0xC060 (SC2_RATELIN)<br />
Reset value: 0x0000 0000<br />
Serial clock linear prescaler register (SCx_RATELIN)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
SC_RATELIN<br />
rw rw rw rw<br />
Bits [3:0] SC_RATELIN: The linear component (LIN) of the clock rate in the equation:<br />
Rate = 12 MHz / ( (LIN + 1) * (2^EXP) )<br />
Doc ID 018587 Rev 2 94/215
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