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<strong>STM32W108C8</strong><br />
Serial interfaces<br />
9.8.4 Serial controller interrupt mode register (SCx_INTMODE)<br />
Table 54.<br />
Address offset: 0xA854 (SC1_INTMODE) and 0xA858 (SC2_INTMODE)<br />
Reset value: 0x0000 0000<br />
Serial controller interrupt mode register (SCx_INTMODE)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
SC_TX<br />
IDLEL<br />
EVEL<br />
SC_TX<br />
FREEL<br />
EVEL<br />
SC_RX<br />
VALLE<br />
VEL<br />
rw rw rw<br />
Bit 2 SC_TXIDLELEVEL: Transmitter idle interrupt mode<br />
0: Edge triggered 1: Level triggered.<br />
Bit 1 SC_TXFREELEVEL: Transmit buffer free interrupt mode<br />
0: Edge triggered 1: Level triggered.<br />
Bit 0 SC_RXVALLEVEL: Receive buffer has data interrupt mode<br />
0: Edge triggered 1: Level triggered.<br />
9.9 SPI master mode registers<br />
9.9.1 Serial data register (SCx_DATA)<br />
Table 55.<br />
Address offset: 0xC83C (SC1_DATA) and 0xC03C (SC2_DATA)<br />
Reset value: 0x0000 0000<br />
Serial data register (SCx_DATA)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
SC_DATA<br />
rw<br />
Bits [7:0] SC_DATA: Transmit and receive data register. Writing to this register adds a byte to the transmit<br />
FIFO. Reading from this register takes the next byte from the receive FIFO and clears the<br />
overrun error bit if it was set.<br />
In UART mode (SC1 only), reading from this register loads the UART status register with the<br />
parity and frame error status of the next byte in the FIFO, and clears these bits if the FIFO is<br />
now empty.<br />
Doc ID 018587 Rev 2 92/215
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