STM32W108C8

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Serial interfaces <strong>STM32W108C8</strong> ● ● Enable top level NVIC interrupts by setting the INT_SCx bit in the INT_CFGSET register. Start the DMA by loading the DMA buffers by setting the SC_TXLODA/B (or SC_RXLODA/B) bits in the SCx_DMACTRL register. A DMA buffer's end address, SCx_TXENDA/B (or SCx_RXENDA/B), can be written while the buffer is loaded or active. This is useful for receiving messages that contain an initial byte count, since it allows software to set the buffer end address at the last byte of the message. As the DMA channel transfers data between the transmit or receive FIFO and a memory buffer, the DMA count register contains the byte offset from the start of the buffer to the address of the next byte that will be written or read. A transmit DMA channel has a single DMA count register (SCx_TXCNT) that applies to whichever transmit buffer is active, but a receive DMA channel has two DMA count registers (SCx_RXCNTA/B), one for each receive buffer. The DMA count register contents are preserved until the corresponding buffer, or either buffer in the case of the transmit DMA count, is loaded, or until the DMA is reset. The receive DMA count register may be written while the corresponding buffer is loaded. If the buffer is not loaded, writing the DMA count register also loads the buffer while preserving the count value written. This feature can simplify handling UART receive errors. The DMA channel stops using a buffer and unloads it when the following is true: (DMA buffer start address + DMA buffer count) > DMA buffer end address Typically a transmit buffer is unloaded after all its data has been sent, and a receive buffer is unloaded after it is filled with data, but writing to the buffer end address or buffer count registers can also cause a buffer to unload early. Serial controller DMA channels include additional features specific to the SPI and UART operation and are described in those sections. 9.8 Serial controller registers 9.8.1 Serial mode register (SCx_MODE) Address offset: 0xC854 (SC1_MODE) and 0xC054 (SC2_MODE) Reset value: 0x0000 0000 Table 51. Serial mode register (SCx_MODE) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SC_MODE rw Bits [1:0] SC_MODE: Serial controller mode. 0: Disabled. 2: SPI mode. 1: UART mode (valid only for SC1). 3: I 2 C mode. 89/215 Doc ID 018587 Rev 2
<strong>STM32W108C8</strong> Serial interfaces 9.8.2 Serial controller interrupt flag register (INT_SCxFLAG) Table 52. Address offset: 0xA808 (INT_SC1FLAG) and 0xA80C (INT_SC2FLAG) Reset value: 0x0000 0000 Serial controller interrupt flag register (INT_SCxFLAG) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reser ved INT_S C1PA RERR INT_S C1FR MERR INT_S CTXU LDB INT_S CTXU LDA INT_S CRXU LDB INT_S CRXU LDA INT_S CNAK INT_S CCMD FIN INT_S CTXFI N INT_SC RXFIN INT_S CTXU ND INT_S CRXO VF INT_S CTXID LE INT_S CTXFR EE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw INT_S CRXVA L Bit 14 INT_SC1PARERR: Parity error received (UART) interrupt pending. Bit 13 INT_SC1FRMERR: Frame error received (UART) interrupt pending. Bit 12 INT_SCTXULDB: DMA transmit buffer B unloaded interrupt pending. Bit 11 INT_SCTXULDA: DMA transmit buffer A unloaded interrupt pending. Bit 10 INT_SCRXULDB: DMA receive buffer B unloaded interrupt pending. Bit 9 INT_SCRXULDA: DMA receive buffer A unloaded interrupt pending. Bit 8 INT_SCNAK: NACK received (I 2 C) interrupt pending. Bit 7 INT_SCCMDFIN: START/STOP command complete (I 2 C) interrupt pending. Bit 6 INT_SCTXFIN: Transmit operation complete (I 2 C) interrupt pending. Bit 5 INT_SCRXFIN: Receive operation complete (I 2 C) interrupt pending. Bit 4 INT_SCTXUND: Transmit buffer underrun interrupt pending. Bit 3 INT_SCRXOVF: Receive buffer overrun interrupt pending. Bit 2 INT_SCTXIDLE: Transmitter idle interrupt pending. Bit 1 INT_SCTXFREE: Transmit buffer free interrupt pending. Bit 0 INT_SCRXVAL: Receive buffer has data interrupt pending. Doc ID 018587 Rev 2 90/215
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STM32W108C8 High-performance, IEEE
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STM32W108C8 Software reset . . . .
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STM32W108C8 9 Serial interfaces . .
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STM32W108C8 10.1.4 Capture/compare
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STM32W108C8 12.1.1 Non-maskable int
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STM32W108C8 Description 1 Descripti
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STM32W108C8 Description 1.2 Overvie
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STM32W108C8 Documentation conventio
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STM32W108C8 Pinout and pin descript
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STM32W108C8 Embedded memory 4 Embed
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STM32W108C8 Embedded memory 6. Seri
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STM32W108C8 Radio frequency module
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STM32W108C8 System modules 6 System
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STM32W108C8 System modules 6.2 Rese
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STM32W108C8 System modules ● PRES
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STM32W108C8 General-purpose timers
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STM32W108C8 Analog-to-digital conve
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STM32W108C8 Interrupts 12 Interrupt
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STM32W108C8 Interrupts Table 122. N
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STM32W108C8 Interrupts Figure 50. P
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STM32W108C8 Interrupts Table 123. N
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STM32W108C8 Interrupts 12.3.2 Top-l
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STM32W108C8 Debug support 13 Debug
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STM32W108C8 Electrical characterist
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STM32W108C8 Package characteristics
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STM32W108C8 Revision history 17 Rev
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STM32W108C8 Index of registers TIMx
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STM32W108C8

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