STM32W108C8

Serial interfaces
STM32W108C8
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Enable top level NVIC interrupts by setting the INT_SCx bit in the INT_CFGSET
register.
Start the DMA by loading the DMA buffers by setting the SC_TXLODA/B (or
SC_RXLODA/B) bits in the SCx_DMACTRL register.
A DMA buffer's end address, SCx_TXENDA/B (or SCx_RXENDA/B), can be written while
the buffer is loaded or active. This is useful for receiving messages that contain an initial
byte count, since it allows software to set the buffer end address at the last byte of the
message.
As the DMA channel transfers data between the transmit or receive FIFO and a memory
buffer, the DMA count register contains the byte offset from the start of the buffer to the
address of the next byte that will be written or read. A transmit DMA channel has a single
DMA count register (SCx_TXCNT) that applies to whichever transmit buffer is active, but a
receive DMA channel has two DMA count registers (SCx_RXCNTA/B), one for each receive
buffer. The DMA count register contents are preserved until the corresponding buffer, or
either buffer in the case of the transmit DMA count, is loaded, or until the DMA is reset.
The receive DMA count register may be written while the corresponding buffer is loaded. If
the buffer is not loaded, writing the DMA count register also loads the buffer while
preserving the count value written. This feature can simplify handling UART receive errors.
The DMA channel stops using a buffer and unloads it when the following is true:
(DMA buffer start address + DMA buffer count) > DMA buffer end address
Typically a transmit buffer is unloaded after all its data has been sent, and a receive buffer is
unloaded after it is filled with data, but writing to the buffer end address or buffer count
registers can also cause a buffer to unload early.
Serial controller DMA channels include additional features specific to the SPI and UART
operation and are described in those sections.
9.8 Serial controller registers
9.8.1 Serial mode register (SCx_MODE)
Address offset: 0xC854 (SC1_MODE) and 0xC054 (SC2_MODE)
Reset value: 0x0000 0000
Table 51.
Serial mode register (SCx_MODE)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SC_MODE
rw
Bits [1:0] SC_MODE: Serial controller mode.
0: Disabled. 2: SPI mode.
1: UART mode (valid only for SC1). 3: I 2 C mode.
89/215 Doc ID 018587 Rev 2