STM32W108C8

Serial interfaces
STM32W108C8
Figure 12.
RTS/CTS flow control connections
STM32W108
Other Device
RXD
TXD
UART Receiver
nRTS
nCTS
UART Transmitter
TXD
RXD
UART Transmitter
nCTS
nRTS
UART Receiver
Table 50.
The UART RTS/CTS flow control options are selected by the SC1_UARTFLOW and
SC1_UARTAUTO bits in the SC1_UARTCFG register (see Table 50). Whenever the
SC1_UARTFLOW bit is set, the UART will not start transmitting a character unless nCTS is
low (asserted). If nCTS transitions to the high state (deasserts) while a character is being
transmitted, transmission of that character continues until it is complete.
If the SC1_UARTAUTO bit is set, nRTS is controlled automatically by hardware: nRTS is put
into the low state (asserted) when the receive FIFO has room for at least two characters,
otherwise is it in the high state (unasserted). If SC1_UARTAUTO is clear, software controls
the nRTS output by setting or clearing the SC1_UARTRTS bit int the SC1_UARTCFG
register. Software control of nRTS is useful if the external serial device cannot stop
transmitting characters promptly when nRTS is set to the high state (deasserted).
SC1_UARTCFG
UART RTS/CTS flow control configurations
SC1_UARTxxx (1)
FLOW AUTO RTS
Pins used
Operating mode
0 - - TXD, RXD No RTS/CTS flow control
1 0 0/1
1 1 -
TXD, RXD,
nCTS, nRTS
TXD, RXD,
nCTS, nRTS
Flow control using RTS/CTS with software control of nRTS:
nRTS controlled by SC1_UARTRTS bit in SC1_UARTCFG register
Flow control using RTS/CTS with hardware control of nRTS:
nRTS is asserted if room for at least 2 characters in receive FIFO
1. The notation xxx means that the corresponding column header below is inserted to form the field name.
9.6.4 DMA
The DMA Channels section describes how to configure and use the serial receive and
transmit DMA channels.
The receive DMA channel has special provisions to record UART receive errors. When the
DMA channel transfers a character from the receive FIFO to a buffer in memory, it checks
the stored parity and frame error status flags. When an error is flagged, the
SC1_RXERRA/B register is updated, marking the offset to the first received character with a
parity or frame error. Similarly if a receive overrun error occurs, the SC1_RXERRA/B
registers mark the error offset. The receive FIFO hardware generates the INT_SCRXOVF
interrupt and DMA status register indicates the error immediately, but in this case the error
87/215 Doc ID 018587 Rev 2