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<strong>STM32W108C8</strong><br />
Serial interfaces<br />
A UART character frame contains, in sequence:<br />
●<br />
●<br />
●<br />
●<br />
The start bit<br />
The least significant data bit<br />
The remaining data bits<br />
If parity is enabled, the parity bit<br />
● The stop bit, or bits, if 2 stop bits are selected.<br />
Figure 10 shows the UART character frame format, with optional bits indicated. Depending<br />
on the options chosen for the character frame, the length of a character frame ranges from 9<br />
to 12 bit times.<br />
Note that asynchronous serial data may have arbitrarily long idle periods between<br />
characters. When idle, serial data (TXD or RXD) is held in the high state. Serial data<br />
transitions to the low state in the start bit at the beginning of a character frame.<br />
Figure 10.<br />
UART character frame format<br />
UART Character Frame Format<br />
(optional sections are in italics )<br />
TXD<br />
or<br />
RXD<br />
Idle time<br />
Start<br />
Bit<br />
Data<br />
Bit 0<br />
Data<br />
Bit 1<br />
Data<br />
Bit 2<br />
Data<br />
Bit 3<br />
Data<br />
Bit 4<br />
Data<br />
Bit 5<br />
Data<br />
Bit 6<br />
Data<br />
Bit 7<br />
Parity<br />
Bit<br />
Stop<br />
Bit<br />
Stop<br />
Bit<br />
Next<br />
Start Bit<br />
or<br />
IdleTime<br />
9.6.2 FIFOs<br />
Characters transmitted and received by the UART are buffered in the transmit and receive<br />
FIFOs that are both 4 entries deep (see Figure 11). When software writes a character to the<br />
SC1_DATA register, it is pushed onto the transmit FIFO. Similarly, when software reads from<br />
the SC1_DATA register, the character returned is pulled from the receive FIFO. If the<br />
transmit and receive DMA channels are used, the DMA channels also write to and read from<br />
the transmit and receive FIFOs.<br />
Figure 11.<br />
UART FIFOs<br />
RXD<br />
Receive Shift Register<br />
Parity/Frame Errors<br />
Transmit Shift Register<br />
TXD<br />
Receive FIFO<br />
SC1_DATA (read)<br />
SC1_UARTSTAT<br />
SC1_DATA (write)<br />
Transmit FIFO<br />
CPU and DMA<br />
Channel Access<br />
9.6.3 RTS/CTS flow control<br />
RTS/CTS flow control, also called hardware flow control, uses two signals (nRTS and nCTS)<br />
in addition to received and transmitted data (see Figure 12). Flow control is used by a data<br />
receiver to prevent buffer overflow, by signaling an external device when it is and is not<br />
allowed to transmit.<br />
Doc ID 018587 Rev 2 86/215
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