STM32W108C8

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Serial interfaces <strong>STM32W108C8</strong> The I 2 C master controller uses just two signals: ● SDA (Serial Data) - bidirectional serial data ● SCL (Serial Clock) - bidirectional serial clock Table 45 lists the GPIO pins used by the SC1 and SC2 I 2 C master controllers. Because the pins are configured as open-drain outputs, they require external pull-up resistors. Table 45. I 2 C Master GPIO Usage Parameter SDA SCL Direction Input / Output Input / Output GPIO configuration Alternate Output (open drain) Alternate Output (open drain) SC1 pin PB1 PB2 SC2 pin PA1 PA2 9.5.1 Setup and configuration The I 2 C controller is enabled by writing 3 to the SCx_MODE register. The I 2 C controller operates only in master mode and supports both Standard (100 kbps) and Fast (400 kbps) I 2 C modes. Address arbitration is not implemented, so multiple master applications are not supported. The I 2 C master controller's serial clock (SCL) is produced by a programmable clock generator. SCL is produced by dividing down 12 MHz according to this equation: Rate = ---------------------------------------- 12MHz ( LIN + 1)x2 EXP EXP is the value written to the SCx_RATEEXP register and LIN is the value written to the SCx_RATELIN register. I2C clock rate programming on page 81 shows the rate settings for Standard-Mode I 2 C (100 kbps) and Fast-Mode I 2 C (400 kbps) operation. Table 46. I 2 C clock rate programming Clock rate SCx_RATELIN SCx_RATEEXP 100 kbps 14 3 375 kbps 15 1 400 kbps 14 1 Note: At 400 kbps, the Philips I 2 C Bus specification requires the minimum low period of SCL to be 1.3 µs, but on the STM32W108 it is 1.25 µs. If a slave device requires strict compliance with SCL timing, the clock rate must be lowered to 375 kbps. 9.5.2 Constructing frames The I 2 C master controller supports generating various frame segments by means of the SC_TWISTART, SC_TWISTOP, SC_TWISEND, and SC_TWIRECV bits in the SCx_TWICTRL1 registers. Figure 47 summarizes these frames. 81/215 Doc ID 018587 Rev 2
<strong>STM32W108C8</strong> Serial interfaces Table 47. I 2 C master frame segments SCx_TWICTRL1 SC_TWIxxxx (1) Frame segments START SEND RECV STOP TWI start segment SCL outSLAVE TWI re-start segment - after transmit or frame with NACK SCL outSLAVE 1 0 0 0 SCL out SDA out SCL out SDA out SDA outSLAVE SDA outSLAVE SCL outSLAVE TWI transmit segment - after (re-)start frame SCL out TX[7] TX[6] TX[5] TX[4] TX[3] TX[2] TX[1] TX[0] SDAout 0 1 0 0 SDA outSLAVE TWI transmit segment – after transmit with ACK (N)ACK SCLoutSLAVE SCL out TX[7] TX[6] TX[5] TX[4] TX[3] TX[2] TX[1] TX[0] SDA out SDAoutSLAVE (N)ACK TWI receive segment – transmit with ACK SCL outSLAVE SCLout SDA out (N)ACK 0 0 1 0 SDA outSLAVE SCL outSLAVE RX[7] RX[6] RX[5] RX[4] RX[3] RX[2] RX[1] RX[0] TWI receive segment - after receive with ACK SCL out RX[7] RX[6] RX[5] RX[4] RX[3] RX[2] RX[1] RX[0] SDA out (N)ACK SDA outSLAVE TWI stop segment - after frame with NACK or stop SCL outSLAVE 0 0 0 1 SCL out SDA out SDA outSLAVE 0 0 0 0 No pending frame segment 1 - - 1 1 1 - - - 1 1 - - - 1 1 Illegal 1. The notation xxx means that the corresponding column header below is inserted to form the field name. Full I 2 C frames have to be constructed by software from individual I 2 C segments. All necessary segment transitions are shown in Figure 9. ACK or NACK generation of an I 2 C Doc ID 018587 Rev 2 82/215
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STM32W108C8 High-performance, IEEE
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STM32W108C8 Software reset . . . .
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STM32W108C8 9 Serial interfaces . .
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STM32W108C8 10.1.4 Capture/compare
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STM32W108C8 12.1.1 Non-maskable int
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STM32W108C8 Description 1 Descripti
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STM32W108C8 Description 1.2 Overvie
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STM32W108C8 Documentation conventio
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STM32W108C8 Pinout and pin descript
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STM32W108C8 Embedded memory 4 Embed
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STM32W108C8 General-purpose timers
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STM32W108C8 Interrupts 12 Interrupt
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STM32W108C8 Interrupts Table 122. N
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STM32W108C8 Interrupts Figure 50. P
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STM32W108C8 Interrupts Table 123. N
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STM32W108C8 Interrupts 12.3.2 Top-l
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STM32W108C8 Debug support 13 Debug
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STM32W108C8 Electrical characterist
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STM32W108C8 Package characteristics
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STM32W108C8 Revision history 17 Rev
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STM32W108C8 Index of registers TIMx
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STM32W108C8

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