STM32W108C8

Serial interfaces
STM32W108C8
The I 2 C master controller uses just two signals:
●
SDA (Serial Data) - bidirectional serial data
● SCL (Serial Clock) - bidirectional serial clock
Table 45 lists the GPIO pins used by the SC1 and SC2 I 2 C master controllers. Because the
pins are configured as open-drain outputs, they require external pull-up resistors.
Table 45.
I 2 C Master GPIO Usage
Parameter SDA SCL
Direction Input / Output Input / Output
GPIO configuration
Alternate Output
(open drain)
Alternate Output
(open drain)
SC1 pin PB1 PB2
SC2 pin PA1 PA2
9.5.1 Setup and configuration
The I 2 C controller is enabled by writing 3 to the SCx_MODE register. The I 2 C controller
operates only in master mode and supports both Standard (100 kbps) and Fast (400 kbps)
I 2 C modes. Address arbitration is not implemented, so multiple master applications are not
supported.
The I 2 C master controller's serial clock (SCL) is produced by a programmable clock
generator. SCL is produced by dividing down 12 MHz according to this equation:
Rate
=
----------------------------------------
12MHz
( LIN + 1)x2 EXP
EXP is the value written to the SCx_RATEEXP register and LIN is the value written to the
SCx_RATELIN register. I2C clock rate programming on page 81 shows the rate settings for
Standard-Mode I 2 C (100 kbps) and Fast-Mode I 2 C (400 kbps) operation.
Table 46.
I 2 C clock rate programming
Clock rate SCx_RATELIN SCx_RATEEXP
100 kbps 14 3
375 kbps 15 1
400 kbps 14 1
Note:
At 400 kbps, the Philips I 2 C Bus specification requires the minimum low period of SCL to be
1.3 µs, but on the STM32W108 it is 1.25 µs. If a slave device requires strict compliance with
SCL timing, the clock rate must be lowered to 375 kbps.
9.5.2 Constructing frames
The I 2 C master controller supports generating various frame segments by means of the
SC_TWISTART, SC_TWISTOP, SC_TWISEND, and SC_TWIRECV bits in the
SCx_TWICTRL1 registers. Figure 47 summarizes these frames.
81/215 Doc ID 018587 Rev 2