STM32W108C8

STM32W108C8
Serial interfaces
9.4.3 DMA
The SPI slave controller must guarantee that there is time to move new transmit data from
the transmit FIFO into the hardware serializer. To provide sufficient time, the SPI slave
controller inserts a byte of padding at the start of every new string of transmit data. After
slave select asserts and the SC_SPIRXVAL bit in the SCx_SPISTAT register gets set at
least once, the following operation holds true until slave select deasserts. Whenever the
transmit FIFO is empty and data is placed into the transmit FIFO, either manually or through
DMA, the SPI hardware inserts a byte of padding onto the front of the transmission as if this
byte was placed there by software. The value of the byte of padding that is inserted is
selected by the SC_SPIRPT bit in the SCx_SPICFG register.
The DMA Channels section describes how to configure and use the serial receive and
transmit DMA channels.
When using the receive DMA channel and nSSEL transitions to the high (deasserted) state,
the active buffer's receive DMA count register (SCx_RXCNTA/B) is saved in the
SCx_RXCNTSAVED register. SCx_RXCNTSAVED is only written the first time nSSEL goes
high after a buffer has been loaded. Subsequent rising edges set a status bit but are
otherwise ignored. The 3-bit field SC_RXSSEL in the SCx_DMASTAT register records what,
if anything, was saved to the SCx_RXCNTSAVED register, and whether or not another
rising edge occurred on nSSEL.
9.4.4 Interrupts
SPI slave controller second level interrupts are generated on the following events:
● Transmit FIFO empty and last character shifted out (depending on SCx_INTMODE,
either the 0 to 1 transition or the high level of SC_SPITXIDLE)
● Transmit FIFO changed from full to not full (depending on SCx_INTMODE, either the 0
to 1 transition or the high level of SC_SPITXFREE)
● Receive FIFO changed from empty to not empty (depending on SCx_INTMODE, either
the 0 to 1 transition or the high level of SC_SPIRXVAL)
● Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)
● Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)
●
Received and lost character while receive FIFO was full (receive overrun error)
● Transmitted character while transmit FIFO was empty (transmit underrun error)
To enable CPU interrupts, set desired interrupt bits in the second level INT_SCxCFG
register, and also enable the top level SCx interrupt in the NVIC by writing the INT_SCx bit
in the INT_CFGSET register.
9.5 Inter-integrated circuit interfaces (I 2 C)
Both STM32W108C8 serial controllers SC1 and SC2 include an Inter-integrated circuit
interface (I 2 C) master controller with the following features:
● Uses only two bidirectional GPIO pins
● Programmable clock frequency (up to 400 kHz)
● Supports both 7-bit and 10-bit addressing
● Compatible with Philips' I 2 C-bus slave devices
Doc ID 018587 Rev 2 80/215