STM32W108C8

Serial interfaces
STM32W108C8
Table 44.
SCx_SPICFG
SPI slave mode formats (continued)
SC_SPIxxx (1)
Frame format
MST ORD PHA POL
nSSEL
0 0 1 1
SCLK in
MOSI in
RX[7]
RX[6]
RX[5]
RX[4]
RX[3]
RX[2]
RX[1]
RX[0]
MISOout
TX[7]
TX[6]
TX[5]
TX[4]
TX[3]
TX[2]
TX[1]
TX[0]
0 1 - - Same as above except LSB first instead of MSB first.
1. The notation xxx means that the corresponding column header below is inserted to form the field name.
9.4.2 Operation
When the slave select (nSSEL) signal is asserted by the master, SPI transmit data is driven
to the output pin MISO, and SPI data is received from the input pin MOSI. The nSSEL pin
has to be asserted to enable the transmit serializer to drive data to the output signal MISO.
A falling edge on nSSEL resets the SPI slave shift registers.
Characters transmitted and received by the SPI slave controller are buffered in the transmit
and receive FIFOs that are both 4 entries deep. When software writes a character to the
SCx_DATA register, it is pushed onto the transmit FIFO. Similarly, when software reads from
the SCx_DATA register, the character returned is pulled from the receive FIFO. If the
transmit and receive DMA channels are used, the DMA channels also write to and read from
the transmit and receive FIFOs.
Characters received are stored in the receive FIFO. Receiving characters sets the
SC_SPIRXVAL bit in the SCx_SPISTAT register, to indicate that characters can be read
from the receive FIFO. Characters received while the receive FIFO is full are dropped, and
the SC_SPIRXOVF bit in the SCx_SPISTAT register is set. The receive FIFO hardware
generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error
condition until the receive FIFO is drained. Once the DMA marks a receive error, two
conditions will clear the error indication: setting the appropriate SC_TX/RXDMARST bit in
the SCx_DMACTRL register, or loading the appropriate DMA buffer after it has unloaded.
Receiving a character causes the serial transmission of a character pulled from the transmit
FIFO. When the transmit FIFO is empty, a transmit underrun is detected (no data in transmit
FIFO) and the INT_SCTXUND bit in the INT_SCxFLAG register is set. Because no
character is available for serialization, the SPI serializer retransmits the last transmitted
character or a busy token (0xFF), determined by the SC_SPIRPT bit in the SCx_SPICFG
register.
When the transmit FIFO and the serializer are both empty, writing a character to the transmit
FIFO clears the SC_SPITXIDLE bit in the SCx_SPISTAT register. This indicates that not all
characters have been transmitted. If characters are written to the transmit FIFO until it is full,
the SC_SPITXFREE bit in the SCx_SPISTAT register is cleared. Shifting out a transmit
character to the MISO pin causes the SC_SPITXFREE bit in the SCx_SPISTAT register to
get set. When the transmit FIFO empties and the last character has been shifted out, the
SC_SPITXIDLE bit in the SCx_SPISTAT register is set.
79/215 Doc ID 018587 Rev 2