STM32W108C8

STM32W108C8
Serial interfaces
Table 43.
SPI slave GPIO usage
Parameter MOSI MISO SCLK nSSEL
Direction Input Output Input Input
GPIO
configuration
Input
Alternate Output
(push-pull)
Input
Input
SC1 pin PB2 PB1 PB3 PB4
SC2 pin PA0 PA1 PA2 PA3
9.4.1 Setup and configuration
Both serial controllers, SC1 and SC2, support SPI slave mode. SPI slave mode is enabled
by the following register settings:
● The serial controller mode register, SCx_MODE, is ‘2’.
● The SC_SPIMST bit in the SPI configuration register, SCx_SPICFG, is ‘0’.
The SPI slave controller receives its clock from an external SPI master device and supports
rates up to 5 Mbps.
The SPI slave controller supports various frame formats depending upon the clock polarity
(SC_SPIPOL), clock phase (SC_SPIPHA), and direction of data (SC_SPIORD) (see Table 8
6). The SC_SPIPOL, SC_SPIPHA, and SC_SPIORD bits are defined within the
SCx_SPICFG registers.
Table 44.
SPI slave mode formats
SCx_SPICFG
SC_SPIxxx (1)
Frame format
MST ORD PHA POL
nSSEL
0 0 0 0
SCLK in
MOSI in
RX[7]
RX[6]
RX[5]
RX[4]
RX[3]
RX[2]
RX[1]
RX[0]
MISOout
TX[7]
TX[6]
TX[5]
TX[4]
TX[3]
TX[2]
TX[1]
TX[0]
0 0 0 1
SCLK in
MOSI in
RX[7]
RX[6]
RX[5]
RX[4]
RX[3]
RX[2]
RX[1]
RX[0]
MISOout
TX[7]
TX[6]
TX[5]
TX[4]
TX[3]
TX[2]
TX[1]
TX[0]
nSSEL
0 0 1 0
SCLK in
MOSI in
RX[7]
RX[6]
RX[5]
RX[4]
RX[3]
RX[2]
RX[1]
RX[0]
MISOout
TX[7]
TX[6]
TX[5]
TX[4]
TX[3]
TX[2]
TX[1]
TX[0]
Doc ID 018587 Rev 2 78/215