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Serial interfaces<br />
<strong>STM32W108C8</strong><br />
Every time an automatic character transmission starts, a transmit underrun is detected as<br />
there is no data in transmit FIFO, and the INT_SCTXUND bit in the INT_SC2FLAG register<br />
is set. After automatic character transmission is disabled, no more new characters are<br />
received. The receive FIFO holds characters just received.<br />
Note:<br />
The Receive DMA complete event does not always mean the receive FIFO is empty.<br />
The DMA Channels section describes how to configure and use the serial receive and<br />
transmit DMA channels.<br />
9.3.3 Interrupts<br />
SPI master controller second level interrupts are generated by the following events:<br />
● Transmit FIFO empty and last character shifted out (depending on SCx_INTMODE,<br />
either the 0 to 1 transition or the high level of SC_SPITXIDLE)<br />
● Transmit FIFO changed from full to not full (depending on SCx_INTMODE, either the 0<br />
to 1 transition or the high level of SC_SPITXFREE)<br />
● Receive FIFO changed from empty to not empty (depending on SCx_INTMODE, either<br />
the 0 to 1 transition or the high level of SC_SPIRXVAL)<br />
● Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)<br />
● Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)<br />
●<br />
Received and lost character while receive FIFO was full (receive overrun error)<br />
● Transmitted character while transmit FIFO was empty (transmit underrun error)<br />
To enable CPU interrupts, set the desired interrupt bits in the second level INT_SCxCFG<br />
register, and enable the top level SCx interrupt in the NVIC by writing the INT_SCx bit in the<br />
INT_CFGSET register.<br />
9.4 SPI slave mode<br />
Both SC1 and SC2 SPI controllers include a SPI slave controller with these features:<br />
● Full duplex operation<br />
● Up to 5 Mbps data transfer rate<br />
● Programmable clock polarity and clock phase<br />
● Selectable data shift direction (either LSB or MSB first)<br />
● Slave select input<br />
The SPI slave controller uses four signals:<br />
● MOSI (Master Out, Slave In) - inputs serial data from the master<br />
● MISO (Master In, Slave Out) - outputs serial data to the master<br />
● SCLK (Serial Clock) - clocks data transfers on MOSI and MISO<br />
● nSSEL (Slave Select) - enables serial communication with the slave<br />
The GPIO pins that can be assigned to these signals are shown in Table 43.<br />
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