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<strong>STM32W108C8</strong><br />
Serial interfaces<br />
Table 42.<br />
SPI master mode formats (continued)<br />
SCx_SPICFG<br />
SC_SPIxxx (1)<br />
Frame formats<br />
MST ORD PHA POL<br />
1 0 1 0<br />
SCLK out<br />
MOSI out<br />
TX[7]<br />
TX[6]<br />
TX[5]<br />
TX[4]<br />
TX[3]<br />
TX[2]<br />
TX[1]<br />
TX[0]<br />
MISO in<br />
RX[7]<br />
RX[6]<br />
RX[5]<br />
RX[4]<br />
RX[3]<br />
RX[2]<br />
RX[1]<br />
RX[0]<br />
1 0 1 1<br />
SCLK out<br />
MOSI out<br />
TX[7]<br />
TX[6]<br />
TX[5]<br />
TX[4]<br />
TX[3]<br />
TX[2]<br />
TX[1]<br />
TX[0]<br />
MISO in<br />
RX[7]<br />
RX[6]<br />
RX[5]<br />
RX[4]<br />
RX[3]<br />
RX[2]<br />
RX[1]<br />
RX[0]<br />
1 1 - - Same as above except data is sent LSB first instead of MSB first.<br />
1. The notation xxx means that the corresponding column header below is inserted to form the field name.<br />
9.3.2 Operation<br />
Characters transmitted and received by the SPI master controller are buffered in transmit<br />
and receive FIFOs that are both 4 entries deep. When software writes a character to the<br />
SCx_DATA register, the character is pushed onto the transmit FIFO. Similarly, when<br />
software reads from the SCx_DATA register, the character returned is pulled from the<br />
receive FIFO. If the transmit and receive DMA channels are used, they also write to and<br />
read from the transmit and receive FIFOs.<br />
When the transmit FIFO and the serializer are both empty, writing a character to the transmit<br />
FIFO clears the SC_SPITXIDLE bit in the SCx_SPISTAT register. This indicates that some<br />
characters have not yet been transmitted. If characters are written to the transmit FIFO until<br />
it is full, the SC_SPITXFREE bit in the SCx_SPISTAT register is cleared. Shifting out a<br />
character to the MOSI pin sets the SC_SPITXFREE bit in the SCx_SPISTAT register. When<br />
the transmit FIFO empties and the last character has been shifted out, the SC_SPITXIDLE<br />
bit in the SCx_SPISTAT register is set.<br />
Characters received are stored in the receive FIFO. Receiving characters sets the<br />
SC_SPIRXVAL bit in the SCx_SPISTAT register, indicating that characters can be read from<br />
the receive FIFO. Characters received while the receive FIFO is full are dropped, and the<br />
SC_SPIRXOVF bit in the SCx_SPISTAT register is set. The receive FIFO hardware<br />
generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error<br />
condition until the receive FIFO is drained. Once the DMA marks a receive error, two<br />
conditions will clear the error indication: setting the appropriate SC_TX/RXDMARST bit in<br />
the SCx_DMACTRL register, or loading the appropriate DMA buffer after it has unloaded.<br />
To receive a character, you must transmit a character. If a long stream of receive characters<br />
is expected, a long sequence of dummy transmit characters must be generated. To avoid<br />
software or transmit DMA initiating these transfers and consuming unnecessary bandwidth,<br />
the SPI serializer can be instructed to retransmit the last transmitted character or to transmit<br />
a busy token (0xFF), which is determined by the SC_SPIRPT bit in the SCx_SPICFG<br />
register. This functionality can only be enabled or disabled when the transmit FIFO is empty<br />
and the transmit serializer is idle, indicated by a cleared SC_SPITXIDLE bit in the<br />
SCx_SPISTAT register.<br />
Doc ID 018587 Rev 2 76/215