STM32W108C8

STM32W108C8
Serial interfaces
Table 39.
SC1 GPIO usage and configuration
Interface PB1 PB2 PB3 PB4
SPI - Master
SC1MOSI alternate
output (push-pull)
SC1MISO input
SC1SCLK alternate
output (push-pull);
special SCLK mode
(not used)
SPI - Slave
SC1MISO alternate
output (push-pull)
SC1MOSI input SC1SCLK input SC1nSSEL input
I 2 C - Master
SC1SDA alternate
output (open-drain)
SC1SCL alternate
output (open-drain)
(not used)
(not used)
UART
TXD alternate
output (push-pull)
RXD input nCTS input (1)
nRTS alternate
output (push-pull)
(1)
1. used if RTS/CTS hardware flow control is enabled.
Table 40.
SC2 GPIO usage and configuration
Interface PA0 PA1 PA2 PA3
SPI - Master
SC2MOSI
Alternate Output
(push-pull)
SC2MISO Input
SC2SCLK
Alternate Output
(push-pull), special
SCLK mode
(not used)
SPI - Slave
I 2 C - Master
SC2MOSI
Alternate Output
(push-pull)
(not used)
SC2MISO Input SC2SCLK Input SC2nSSEL Input
SC2SDA Alternate
Output (open-drain)
SC2SCL Alternate
Output (open-drain)
(not used)
9.3 SPI master mode
The SPI master controller has the following features:
●
●
●
●
●
Full duplex operation
Programmable clock frequency (6 MHz max.)
Programmable clock polarity and phase
Selectable data shift direction (either LSB or MSB first)
Receive and transmit FIFOs
● Receive and transmit DMA channels
The SPI master controller uses the three signals:
● MOSI (Master Out, Slave In) - outputs serial data from the master
● MISO (Master In, Slave Out) - inputs serial data from a slave
● SCLK (Serial Clock) - outputs the serial clock used by MOSI and MISO
The GPIO pins used for these signals are shown in Table 41. Additional outputs may be
needed to drive the nSSEL signals on slave devices.
Doc ID 018587 Rev 2 74/215