STM32W108C8

STM32W108C8
General-purpose input/outputs
8.5 General-purpose input / output (GPIO) registers
8.5.1 Port x configuration register (Low) (GPIO_PxCFGL)
Table 26.
Address offset: 0xB000 (GPIO_PACFGL), 0xB400 (GPIO_PBCFGL) and 0xB800
(GPIO_PCCFGL)
Reset value: 0x0000 4444
Port x configuration register (Low) (GPIO_PxCFGL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Px3_CFG Px2_CFG Px1_CFG Px0_CFG
rw rw rw rw
Bits [15:12] Px3_CFG: GPIO configuration control.
0x0: Analog, input or output (GPIO_PxIN always reads 1).
0x1: Output, push-pull (GPIO_PxOUT controls the output).
0x4: Input, floating.
0x5: Output, open-drain (GPIO_PxOUT controls the output).
0x8: Input, pulled up or down (selected by GPIO_PxOUT: 0 = pull-down, 1 = pull-up).
0x9: Alternate output, push-pull (peripheral controls the output).
0xB: Alternate output SPI SCLK, push-pull (only for SPI master mode SCLK).
0xD: Alternate output, open-drain (peripheral controls the output).
Bits [11:8] Px2_CFG: GPIO configuration control: see Px3_CFG above.
Bits [7:4] Px1_CFG: GPIO configuration control: see Px3_CFG above.
Bits [3:0] Px0_CFG: GPIO configuration control: see Px3_CFG above.
8.5.2 Port x configuration register (High) (GPIO_PxCFGH)
Table 27.
Address offset: 0xB004 (GPIO_PACFGH), 0xB404 (GPIO_PBCFGH) and 0xB804
(GPIO_PCCFGH)
Reset value: 0x0000 4444
Port x configuration register (High) (GPIO_PxCFGH)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Px7_CFG Px6_CFG Px5_CFG Px4_CFG
rw rw rw rw
Doc ID 018587 Rev 2 64/215