STM32W108C8

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General-purpose input/outputs STM32W108C8 that GPIO activity caused a wake event, but not which specific GPIO was responsible. Instead, software should read the state of the GPIOs on waking to determine the cause of the event. The register GPIO_WAKEFILT contains bits to enable digital filtering of the external wakeup event sources: the GPIO pins, SC1 activity, SC2 activity, and IRQD. The digital filter operates by taking samples based on the (nominal) 10 kHz RC oscillator. If three samples in a row all have the same logic value, and this sampled logic value is different from the logic value seen upon entering sleep, the filter outputs a wakeup event. In order to use GPIO pins to wake the STM32W108C8 from deep sleep, the GPIO_WAKE bit in the WAKE_SEL register must be set. Waking up from GPIO activity does not work with pins configured for analog mode since the digital logic input is always set to 1 when in analog mode. Refer to Section 6: System modules on page 32 for information on the STM32W108C8's power management and sleep modes. 8.2 External interrupts The STM32W108C8 can use up to four external interrupt sources (IRQA, IRQB, IRQC, and IRQD), each with its own top level NVIC interrupt vector. Since these external interrupt sources connect to the standard GPIO input path, an external interrupt pin may simultaneously be used by a peripheral device or even configured as an output. Analog mode is the only GPIO configuration that is not compatible with using a pin as an external interrupt. External interrupts have individual triggering and filtering options selected using the registers GPIO_INTCFGA, GPIO_INTCFGB, GPIO_INTCFGC, and GPIO_INTCFGD. The bit field GPIO_INTMOD of the GPIO_INTCFGx register enables IRQx's second level interrupt and selects the triggering mode: 0 is disabled; 1 for rising edge; 2 for falling edge; 3 for both edges; 4 for active high level; 5 for active low level. The minimum width needed to latch an unfiltered external interrupt in both level- and edge-triggered mode is 80 ns. With the digital filter enabled (the GPIO_INTFILT bit in the GPIO_INTCFGx register is set), the minimum width needed is 450 ns. The register INT_GPIOFLAG is the second-level interrupt flag register that indicates pending external interrupts. Writing 1 to a bit in the INT_GPIOFLAG register clears the flag while writing 0 has no effect. If the interrupt is level-triggered, the flag bit is set again immediately after being cleared if its input is still in the active state. Two of the four external interrupts, IRQA and IRQB, have fixed pin assignments. The other two external interrupts, IRQC and IRQD, can use any GPIO pin. The GPIO_IRQCSEL and GPIO_IRQDSEL registers specify the GPIO pins assigned to IRQC and IRQD, respectively. Table 24 shows how the GPIO_IRQCSEL and GPIO_IRQDSEL register values select the GPIO pin used for the external interrupt. Table 24. IRQC/D GPIO selection GPIO_IRQxSEL GPIO GPIO_IRQxSE L GPIO GPIO_IRQxSE L GPIO 0 PA0 8 PB0 16 PC0 1 PA1 9 PB1 17 PC1 2 PA2 10 PB2 18 PC2 61/215 Doc ID 018587 Rev 2
STM32W108C8 General-purpose input/outputs Table 24. GPIO_IRQxSEL IRQC/D GPIO selection (continued) GPIO GPIO_IRQxSE L GPIO GPIO_IRQxSE L GPIO 3 PA3 11 PB3 19 PC3 4 PA4 12 PB4 20 PC4 5 PA5 13 PB5 21 PC5 6 PA6 14 PB6 22 PC6 7 PA7 15 PB7 23 PC7 In some cases, it may be useful to assign IRQC or IRQD to an input also in use by a peripheral, for example to generate an interrupt from the slave select signal (nSSEL) in an SPI slave mode interface. Refer to Section 12: Interrupts on page 174 for further information regarding the STM32W108C8 interrupt system. 8.3 Debug control and status Two GPIO registers are largely concerned with debugger functions. GPIO_DBGCFG can disable debugger operation, but has other miscellaneous control bits as well. GPIO_DBGSTAT, a read-only register, returns status related to debugger activity (GPIO_FORCEDBG and GPIO_SWEN), as well a flag (GPIO_BOOTMODE) indicating whether nBOOTMODE was asserted at the last power-on or NRST-based reset. 8.4 GPIO alternate functions Table 25 lists the GPIO alternate functions. Table 25. GPIO signal assignments GPIO Analog Alternate function Input Output current drive PA0 PA1 PA2 PA3 TIM2_CH1 (1) , SC2MOSI TIM2_CH3 (1) , SC2MISO, SC2SDA TIM2_CH4 (1) , SC2SCLK, SC2SCL TIM2_CH2 (1) , TRACECLK TIM2_CH1 (1) , SC2MOSI TIM2_CH3 (1) , SC2MISO, SC2SDA TIM2_CH4 (1) , SC2SCLK TIM2_CH2 (1) , SC2nSSEL Standard Standard Standard Standard PA4 ADC4 PTI_EN, TRACEDATA2 Standard PA5 ADC5 PTI_DATA, TRACEDATA3 nBOOTMODE (2) Standard PA6 TIM1_CH3 TIM1_CH3 High PA7 TIM1_CH4, REG_EN (3) TIM1_CH4 High Doc ID 018587 Rev 2 62/215
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STM32W108C8 High-performance, IEEE
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STM32W108C8 Software reset . . . .
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STM32W108C8 9 Serial interfaces . .
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STM32W108C8 10.1.4 Capture/compare
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STM32W108C8 12.1.1 Non-maskable int
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STM32W108C8 General-purpose timers
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STM32W108C8 Analog-to-digital conve
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STM32W108C8 Interrupts 12 Interrupt
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STM32W108C8 Interrupts Table 122. N
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STM32W108C8 Interrupts Figure 50. P
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STM32W108C8 Interrupts Table 123. N
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STM32W108C8 Interrupts 12.3.2 Top-l
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STM32W108C8 Debug support 13 Debug
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STM32W108C8 Electrical characterist
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STM32W108C8 Package characteristics
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STM32W108C8 Revision history 17 Rev
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STM32W108C8 Index of registers TIMx
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STM32W108C8

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