STM32W108C8
STM32W108C8 STM32W108C8
General-purpose input/outputs STM32W108C8 Table 21. GPIO configuration modes (continued) GPIO mode GPIO_PxCFGH/L Description Alternate Output (opendrain) Alternate Output (pushpull) SPI SCLK Mode 0xD 0xB Open-drain output. An onboard peripheral controls the output. If a pull up is required, it must be external. Push-pull output mode only for SPI master mode SCLK pins. If a GPIO has two peripherals that can be the source of alternate output mode data, then other registers in addition to GPIO_PxCFGH/L determine which peripheral controls the output. Several GPIOs share an alternate output with Timer 2 and the Serial Controllers. Bits in Timer 2's TIM2_OR register control routing Timer 2 outputs to different GPIOs. Bits in Timer 2's TIM2_CCER register enable Timer 2 outputs. When Timer 2 outputs are enabled they override Serial Controller outputs. Table 22 indicates the GPIO mapping for Timer 2 outputs depending on the bits in the register TIM2_OR. Refer to Section 10: General-purpose timers on page 109 for complete information on timer configuration. Table 22. Timer 2 output For outputs assigned to the serial controllers, the serial interface mode registers (SCx_MODE) determine how the GPIO pins are used. The alternate outputs of PA4 and PA5 can either provide packet trace data (PTI_EN and PTI_DATA), or synchronous CPU trace data (TRACEDATA2 and TRACEDATA3). If a GPIO does not have an associated peripheral in alternate output mode, its output is set to 0. 8.1.3 Forced functions Timer 2 output configuration controls Option register bit GPIO mapping selected by TIM2_OR bit 0 1 TIM2_CH1 TIM2_OR[4] PA0 PB1 TIM2_CH2 TIM2_OR[5] PA3 PB2 TIM2_CH3 TIM2_OR[6] PA1 PB3 TIM2_CH4 TIM2_OR[7] PA2 PB4 Note: For some GPIOs the GPIO_PxCFGH/L configuration may be overridden. Table 23 shows the GPIOs that can have different functions forced on them regardless of the GPIO_PxCFGH/L registers. The DEBUG_DIS bit in the GPIO_DBGCFG register can disable the Serial Wire/JTAG debugger interface. When this bit is set, all debugger-related pins (PC0, PC2, PC3, PC4) behave as standard GPIO. 57/215 Doc ID 018587 Rev 2
STM32W108C8 General-purpose input/outputs Table 23. GPIO forced functions GPIO Override condition Forced function Forced signal PA7 GPIO_EXTREGEN bit set in the GPIO_DBGCFG register Open-drain output REG_EN PC0 Debugger interface is active in JTAG mode Input with pull up JRST PC2 Debugger interface is active in JTAG mode Push-pull output JTDO PC3 Debugger interface is active in JTAG mode Input with pull up JDTI PC4 Debugger interface is active in JTAG mode Input with pull up JTMS PC4 Debugger interface is active in Serial Wire mode Bidirectional (push-pull output or floating input) controlled by debugger interface SWDIO 8.1.4 Reset A full chip reset is one due to power on (low or high voltage), the NRST pin, the watchdog, or the SYSRESETREQ bit. A full chip reset affects the GPIO configuration as follows: ● ● ● 8.1.5 nBOOTMODE The GPIO_PxCFGH/L configurations of all pins are configured as floating inputs. The GPIO_EXTREGEN bit is set in the GPIO_DBGCFG register, which overrides the normal configuration for PA7. The GPIO_DEBUGDIS bit in the GPIO_DBGCFG register is cleared, allowing Serial Wire/JTAG access to override the normal configuration of PC0, PC2, PC3, and PC4. nBOOTMODE is a special alternate function of PA5 that is active only during a pin reset (NRST) or a power-on-reset of the always-powered domain (POR_HV). If nBOOTMODE is asserted (pulled or driven low) when coming out of reset, the processor starts executing an embedded serial boot loader instead of its normal program. While in reset and during the subsequent power-on-reset startup delay (512 high-frequency RC oscillator periods), PA5 is automatically configured as an input with a pull-up resistor. At the end of this time, the STM32W108C8 samples nBOOTMODE: a high level selects normal startup, and a low level selects the boot loader. After nBOOTMODE has been sampled, PA5 is configured as a floating input. The GPIO_BOOTMODE bit in the GPIO_DBGSTAT register captures the state of nBOOTMODE so that software may act on this signal if required. Note: To avoid inadvertently asserting nBOOTMODE, PA5's capacitive load should not exceed 252 pF. Doc ID 018587 Rev 2 58/215
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<strong>STM32W108C8</strong><br />
General-purpose input/outputs<br />
Table 23.<br />
GPIO forced functions<br />
GPIO Override condition Forced function Forced signal<br />
PA7<br />
GPIO_EXTREGEN bit set in the<br />
GPIO_DBGCFG register<br />
Open-drain output<br />
REG_EN<br />
PC0 Debugger interface is active in JTAG mode Input with pull up JRST<br />
PC2 Debugger interface is active in JTAG mode Push-pull output JTDO<br />
PC3 Debugger interface is active in JTAG mode Input with pull up JDTI<br />
PC4 Debugger interface is active in JTAG mode Input with pull up JTMS<br />
PC4<br />
Debugger interface is active in Serial Wire<br />
mode<br />
Bidirectional (push-pull<br />
output or floating input)<br />
controlled by debugger<br />
interface<br />
SWDIO<br />
8.1.4 Reset<br />
A full chip reset is one due to power on (low or high voltage), the NRST pin, the watchdog, or<br />
the SYSRESETREQ bit. A full chip reset affects the GPIO configuration as follows:<br />
●<br />
●<br />
●<br />
8.1.5 nBOOTMODE<br />
The GPIO_PxCFGH/L configurations of all pins are configured as floating inputs.<br />
The GPIO_EXTREGEN bit is set in the GPIO_DBGCFG register, which overrides the<br />
normal configuration for PA7.<br />
The GPIO_DEBUGDIS bit in the GPIO_DBGCFG register is cleared, allowing Serial<br />
Wire/JTAG access to override the normal configuration of PC0, PC2, PC3, and PC4.<br />
nBOOTMODE is a special alternate function of PA5 that is active only during a pin reset<br />
(NRST) or a power-on-reset of the always-powered domain (POR_HV). If nBOOTMODE is<br />
asserted (pulled or driven low) when coming out of reset, the processor starts executing an<br />
embedded serial boot loader instead of its normal program.<br />
While in reset and during the subsequent power-on-reset startup delay (512 high-frequency<br />
RC oscillator periods), PA5 is automatically configured as an input with a pull-up resistor. At<br />
the end of this time, the <strong>STM32W108C8</strong> samples nBOOTMODE: a high level selects normal<br />
startup, and a low level selects the boot loader. After nBOOTMODE has been sampled, PA5<br />
is configured as a floating input. The GPIO_BOOTMODE bit in the GPIO_DBGSTAT register<br />
captures the state of nBOOTMODE so that software may act on this signal if required.<br />
Note:<br />
To avoid inadvertently asserting nBOOTMODE, PA5's capacitive load should not exceed<br />
252 pF.<br />
Doc ID 018587 Rev 2 58/215
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