STM32W108C8

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System modules STM32W108C8 In normal operation an application may request one of two low power modes through program execution: ● Idle Sleep is achieved by executing a WFI instruction whilst the SLEEPDEEP bit in the Cortex System Control register (SCS_SCR) is clear. This puts the CPU into an idle state where execution is suspended until an interrupt occurs. This is indicated by the state at the bottom of the diagram. Power is maintained to the core logic of the STM32W108C8 during the Idle Sleeping state. ● Deep sleep is achieved by executing a WFI instruction with the SLEEPDEEP bit in SCS_SCR set. This triggers the state transitions around the main loop of the diagram, resulting in powering down the STM32W108C8's core logic, and leaving only the always-on domain powered. Wake up is triggered when one of the pre-determined events occurs. If a deep sleep is requested the STM32W108C8 first enters a pre-deep sleep state. This state prevents any section of the chip from being powered off or reset until the SWJ goes idle (by clearing CSYSPWRUPREQ). This pre-deep sleep state ensures debug operations are not interrupted. In the deep sleep state the STM32W108C8 waits for a wake up event which will return it to the running state. In powering up the core logic the ARM® Cortex-M3 is put through a reset cycle and ST software restores the stack and application state to the point where deep sleep was invoked. 6.5.3 Further options for deep sleep By default, the low-frequency internal RC oscillator (OSCRC) is running during deep sleep (known as deep sleep 1). To conserve power, OSCRC can be turned off during deep sleep. This mode is known as deep sleep 2. Since the OSCRC is disabled, the sleep timer and watchdog timer do not function and cannot wake the chip unless the low-frequency 32.768 kHz crystal oscillator is used. Non-timer based wake sources continue to function. Once a wake event occurs, the OSCRC restarts and becomes enabled. 6.5.4 Use of debugger with sleep modes The debugger communicates with the STM32W108C8 using the SWJ. When the debugger is connected, the CDBGPWRUPREQ bit in the debug port in the SWJ is set, the STM32W108C8 will only enter deep sleep 0 (the Emulated Deep Sleep state). The CDBGPWRUPREQ bit indicates that a debug tool is connected to the chip and therefore there may be debug state in the system debug components. To maintain the state in the system debug components only deep sleep 0 may be used, since deep sleep 0 will not cause a power cycle or reset of the core domain. The CSYSPWRUPREQ bit in the debug port in the SWJ indicates that a debugger wants to access memory actively in the STM32W108C8. Therefore, whenever the CSYSPWRUPREQ bit is set while the STM32W108C8 is awake, the STM32W108C8 cannot enter deep sleep until this bit is cleared. This ensures the STM32W108C8 does not disrupt debug communication into memory. Clearing both CSYSPWRUPREQ and CDBGPWRUPREQ allows the STM32W108C8 to achieve a true deep sleep state (deep sleep 1 or 2). Both of these signals also operate as wake sources, so that when a debugger connects to the STM32W108C8 and begins accessing the chip, the STM32W108C8 automatically comes out of deep sleep. When the 51/215 Doc ID 018587 Rev 2
STM32W108C8 System modules debugger initiates access while the STM32W108C8 is in deep sleep, the SWJ intelligently holds off the debugger for a brief period of time until the STM32W108C8 is properly powered and ready. For more information regarding the SWJ and the interaction of debuggers with deep sleep, contact ST support for Application Notes and ARM® CoreSight documentation. 6.6 Security accelerator The STM32W108C8 contains a hardware AES encryption engine accessible from the ARM® Cortex-M3. NIST-based CCM, CCM*, CBC-MAC, and CTR modes are implemented in hardware. These modes are described in the IEEE 802.15.4-2003 specification, with the exception of CCM*, which is described in the ZigBee Security Services Specification 1.0. Doc ID 018587 Rev 2 52/215
Page 1 and 2: STM32W108C8 High-performance, IEEE
Page 3 and 4: STM32W108C8 Software reset . . . .
Page 5 and 6: STM32W108C8 9 Serial interfaces . .
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STM32W108C8 Serial interfaces Bit 2
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STM32W108C8 Serial interfaces Bits
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STM32W108C8 Serial interfaces 9.13.
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STM32W108C8 Serial interfaces 9.13.
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STM32W108C8 General-purpose timers
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STM32W108C8 Interrupts 12 Interrupt
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STM32W108C8 Interrupts Table 122. N
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STM32W108C8 Interrupts Figure 50. P
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STM32W108C8 Interrupts Table 123. N
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STM32W108C8 Interrupts 12.3.2 Top-l
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STM32W108C8 Debug support 13 Debug
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STM32W108C8 Electrical characterist
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STM32W108C8 Package characteristics
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STM32W108C8 Revision history 17 Rev
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STM32W108C8 Index of registers TIMx
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STM32W108C8

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