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System modules<br />
<strong>STM32W108C8</strong><br />
In normal operation an application may request one of two low power modes through<br />
program execution:<br />
● Idle Sleep is achieved by executing a WFI instruction whilst the SLEEPDEEP bit in the<br />
Cortex System Control register (SCS_SCR) is clear. This puts the CPU into an idle<br />
state where execution is suspended until an interrupt occurs. This is indicated by the<br />
state at the bottom of the diagram. Power is maintained to the core logic of the<br />
<strong>STM32W108C8</strong> during the Idle Sleeping state.<br />
● Deep sleep is achieved by executing a WFI instruction with the SLEEPDEEP bit in<br />
SCS_SCR set. This triggers the state transitions around the main loop of the diagram,<br />
resulting in powering down the <strong>STM32W108C8</strong>'s core logic, and leaving only the<br />
always-on domain powered. Wake up is triggered when one of the pre-determined<br />
events occurs.<br />
If a deep sleep is requested the <strong>STM32W108C8</strong> first enters a pre-deep sleep state. This<br />
state prevents any section of the chip from being powered off or reset until the SWJ goes<br />
idle (by clearing CSYSPWRUPREQ). This pre-deep sleep state ensures debug operations<br />
are not interrupted.<br />
In the deep sleep state the <strong>STM32W108C8</strong> waits for a wake up event which will return it to<br />
the running state. In powering up the core logic the ARM® Cortex-M3 is put through a reset<br />
cycle and ST software restores the stack and application state to the point where deep sleep<br />
was invoked.<br />
6.5.3 Further options for deep sleep<br />
By default, the low-frequency internal RC oscillator (OSCRC) is running during deep sleep<br />
(known as deep sleep 1).<br />
To conserve power, OSCRC can be turned off during deep sleep. This mode is known as<br />
deep sleep 2. Since the OSCRC is disabled, the sleep timer and watchdog timer do not<br />
function and cannot wake the chip unless the low-frequency 32.768 kHz crystal oscillator is<br />
used. Non-timer based wake sources continue to function. Once a wake event occurs, the<br />
OSCRC restarts and becomes enabled.<br />
6.5.4 Use of debugger with sleep modes<br />
The debugger communicates with the <strong>STM32W108C8</strong> using the SWJ.<br />
When the debugger is connected, the CDBGPWRUPREQ bit in the debug port in the SWJ<br />
is set, the <strong>STM32W108C8</strong> will only enter deep sleep 0 (the Emulated Deep Sleep state).<br />
The CDBGPWRUPREQ bit indicates that a debug tool is connected to the chip and<br />
therefore there may be debug state in the system debug components. To maintain the state<br />
in the system debug components only deep sleep 0 may be used, since deep sleep 0 will<br />
not cause a power cycle or reset of the core domain. The CSYSPWRUPREQ bit in the<br />
debug port in the SWJ indicates that a debugger wants to access memory actively in the<br />
<strong>STM32W108C8</strong>. Therefore, whenever the CSYSPWRUPREQ bit is set while the<br />
<strong>STM32W108C8</strong> is awake, the <strong>STM32W108C8</strong> cannot enter deep sleep until this bit is<br />
cleared. This ensures the <strong>STM32W108C8</strong> does not disrupt debug communication into<br />
memory.<br />
Clearing both CSYSPWRUPREQ and CDBGPWRUPREQ allows the <strong>STM32W108C8</strong> to<br />
achieve a true deep sleep state (deep sleep 1 or 2). Both of these signals also operate as<br />
wake sources, so that when a debugger connects to the <strong>STM32W108C8</strong> and begins<br />
accessing the chip, the <strong>STM32W108C8</strong> automatically comes out of deep sleep. When the<br />
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