STM32W108C8

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System modules STM32W108C8 The following source is only available in deep sleep 0 since the SWJ is required to write memory to set this wake source and the SWJ only has access to some registers in deep sleep 0. ● Wake on write to the WAKE_CORE register bit. The Wakeup Recording module monitors all possible wakeup sources. More than one wakeup source may be recorded because events are continually being recorded (not just in deep-sleep), since another event may happen between the first wake event and when the STM32W108C8 wakes up. 49/215 Doc ID 018587 Rev 2
STM32W108C8 System modules 6.5.2 Basic sleep modes The power management state diagram in Figure 6 shows the basic operation of the power management controller. Figure 6. Power management state diagram CDBGPWRUPREQ set DEEP SLEEP CDBGPWRUPREQ cleared EMULATED DEEP SLEEP CDBGPWRUPREQ=0 & CSYSPWRUPREQ=0 CDBGPWRUPREQ=1 & CSYSPWRUPREQ=0 Wake up event OR CSYSPWRUPREQ set (resets the processor) Wake up event (resets the processor) PRE- DEEP SLEEP Deep sleep requested (WFI instruction with SLEEP_DEEP=1) RUNNING CSYSPWRUPREQ & INHIBIT Sleep requested (WFI instruction with SLEEP_DEEP=0) Interrupt IDLE SLEEP Doc ID 018587 Rev 2 50/215
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Page 3 and 4: STM32W108C8 Software reset . . . .
Page 5 and 6: STM32W108C8 9 Serial interfaces . .
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STM32W108C8 Serial interfaces Bit 2
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STM32W108C8 Serial interfaces Bits
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STM32W108C8 Interrupts 12 Interrupt
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STM32W108C8 Interrupts Table 122. N
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STM32W108C8 Debug support 13 Debug
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STM32W108C8 Package characteristics
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STM32W108C8 Revision history 17 Rev
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STM32W108C8 Index of registers TIMx
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STM32W108C8

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