STM32W108C8

STM32W108C8
System modules
Bit 1 SLEEPTMR_CLK10KEN: Enables 10kHz internal RC during deep
Note: Bits are cleared when set to ‘1’.
Bit 0 SLEEPTMR_CLK32KEN: Enables 32kHz external XTAL
Note: Bits are cleared when set to ‘1’.
6.5 Power management
The STM32W108C8's power management system is designed to achieve the lowest deep
sleep current consumption possible while still providing flexible wakeup sources, timer
activity, and debugger operation. The STM32W108C8 has four main sleep modes:
● Idle Sleep: Puts the CPU into an idle state where execution is suspended until any
interrupt occurs. All power domains remain fully powered and nothing is reset.
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6.5.1 Wake sources
Deep Sleep 1: The primary deep sleep state. In this state, the core power domain is
fully powered down and the sleep timer is active
Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to
save power. In this mode the sleep timer cannot wakeup the STM32W108C8.
Deep Sleep 0 (also known as Emulated Deep Sleep): The chip emulates a true deep
sleep without powering down the core domain. Instead, the core domain remains
powered and all peripherals except the system debug components (ITM, DWT, FPB,
NVIC) are held in reset. The purpose of this sleep state is to allow STM32W108C8
software to perform a deep sleep cycle while maintaining debug configuration such as
breakpoints.
When in deep sleep the STM32W108C8 can be returned to the running state in a number of
ways, and the wake sources are split depending on deep sleep 1 or deep sleep 2.
The following wake sources are available in both deep sleep 1 and 2.
● Wake on GPIO activity: Wake due to change of state on any GPIO.
● Wake on serial controller 1: Wake due to a change of state on GPIO Pin PB2.
● Wake on serial controller 2: Wake due to a change of state on GPIO Pin PA2.
● Wake on IRQD: Wake due to a change of state on IRQD. Since IRQD can be
configured to point to any GPIO, this wake source is another means of waking on any
GPIO activity.
● Wake on setting of CDBGPWRUPREQ: Wake due to setting the CDBGPWRUPREQ bit
in the debug port in the SWJ.
● Wake on setting of CSYSPWRUPREQ: Wake due to setting the CSYSPWRUPREQ bit
in the debug port in the SWJ.
The following sources are only available in deep sleep 1 since the sleep timer is not active in
deep sleep 2.
● Wake on sleep timer compare A.
● Wake on sleep timer compare B.
● Wake on sleep timer wrap.
Doc ID 018587 Rev 2 48/215