STM32W108C8

System modules
STM32W108C8
Bit 2 INT_ SLEEPTMR CMPB: Sleep timer compare B
Note: Bits are cleared when set to ‘1’.
Bit 1 INT_SLEEPTMRCMPA: Sleep timer compare A
Note: Bits are cleared when set to ‘1’.
Bit 0 INT_SLEEPTMRWRAP: Sleep timer overflow
Note: Bits are cleared when set to ‘1’.
Sleep timer interrupt mask register (INT_SLEEPTMRCFG)
Address: 0x4000 A054
Reset value: 0x0000 0000
Table 18. Sleep timer interrupt mask register (INT_SLEEPTMRCFG)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
INT_
SLEEP
TMR
CMPB
INT_
SLEEP
TMR
CMPA
INT_
SLEEP
TMR
WRAP
r rw rw rw
Bit 2 INT_ SLEEPTMR CMPB: Sleep timer compare B
Bit 1 INT_SLEEPTMRCMPA: Sleep timer compare A
Bit 0 INT_SLEEPTMRWRAP: Sleep timer overflow
Table 19.
Sleep timer clock source enables (SLEEPTMR_CLKEN)
This timer controls the low power clock gated modes.
Clearing CLKRC_EN before executing WFE with SLEEPDEEP bit set in the NVIC System
control register causes DEEP_SLEEP2 to be entered. Setting this bit causes
DEEP_SLEEP1 to be entered.
Address: 0x4000 0008
Reset value: 0x0000 0002
Sleep timer clock source enables (SLEEPTMR_CLKEN)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SLEEP
TMR_
CLK10K
EN
SLEEP
TMR_
CLK32K
EN
r rw rw
47/215 Doc ID 018587 Rev 2