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System modules<br />
<strong>STM32W108C8</strong><br />
Bits [15:0] SLEEPTMR_CMPAH_FIELD:<br />
Sleep timer compare A high value [31:16].<br />
Sleep timer compare value, writing updates COMP_A_H (directly) and COMP_A_L (from<br />
hold register).<br />
Can only be changed when the ENABLE bit (bit 11 of SLEEP_CONFIG register) is set to ‘0’.<br />
If changed when the ENABLE bit is set to ‘1’, a spurious interrupt may be generated.<br />
Therefore it is recommended to disable interrupts before changing this register.<br />
Sleep timer compare A low register (SLEEPTMR_CMPAL)<br />
Address:<br />
Reset value:<br />
0x4000 601C<br />
0x0000 FFFF<br />
Table 14.<br />
Sleep timer compare A low register (SLEEPTMR_CMPAL)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
SLEEPTMR_CMPAL<br />
rw<br />
Bits [15:0] SLEEPTMR_CMPAL_FIELD:<br />
Sleep timer compare A low value [15:0].<br />
Writing to this register puts value in hold register until a write to the SLEEPTMR_CMPAH<br />
register.<br />
Can only be changed when the ENABLE bit (bit 11 of SLEEP_CONFIG register) is set to ‘0’.<br />
If changed when the ENABLE bit is set to ‘1’, a spurious interrupt may be generated.<br />
Therefore it is recommended to disable interrupts before changing this register.<br />
Table 15.<br />
Sleep timer compare B high register (SLEEPTMR_CMPBH)<br />
Address: 0x4000 6020<br />
Reset value: 0x0000 FFFF<br />
Sleep timer compare B high register (SLEEPTMR_CMPBH)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
SLEEPTMR_CMPBH<br />
rw<br />
45/215 Doc ID 018587 Rev 2
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