STM32W108C8

System modules
STM32W108C8
Bits [15:0] WDOG_CTRL: Write 0xDEAD to disable or 0xEABE to enable.
Table 10.
Watchdog restart register (WDOG_RESTART)
Write any value to this register to kick-start the watchdog.
Address: 0x4000 6008
Reset value: 0x0000 0000
Sleep timer configuration register (SLEEPTMR_CFG)
This register sets the various options for the Sleep timer.
Address: 0x4000 600C
Reset value: 0x0000 0400
Sleep timer configuration register (SLEEPTMR_CFG)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SLEEP
TMR_
REVER
SE
SLEEP
TMR_
ENABL
E
SLEEP
TMR_
DBGPA
USE
Reserved SLEEPTMR_CLKDIV Reserved
SLEEP
TMR_
CLKSE
L
r rw rw rw r rw r rw
Bit 12 SLEEPTMR_REVERSE:
0: count forward; 1: count backwards.
Only changes when ENABLE bit is set to ‘0’.
Bit 11 SLEEPTMR_ENABLE:
0: disable sleep timer; 1: enable sleep timer.
To change other register bits (REVERSE, CLK_DIV, CLK_SEL), this bit must be set to ‘0’.
Enabling/Disabling latency can be up 2 to 3 clock-periods of selected clock.
Bit 10 SLEEPTMR_DBGPAUSE: Debug Pause
0: The timer continues working in Debug mode.
1: The timer is paused in Debug mode when the CPU is halted.
Bits [7:4] SLEEPTMR_CLKDIV: Sleep timer prescaler setting
Divides clock by 2 N where N = 0 to 15.
Can only be changed when the ENABLE bit is set to ‘0’.
Bit 0 SLEEPTMR_CLKSEL: Clock Select
0: Calibrated 1kHz RC clock (default); 1: 32kHz
Can only be changed when the ENABLE bit is set to ‘0’.
Sleep timer count high register (SLEEPTMR_CNTH)
Address: 0x4000 6010
Reset value: 0x0000 0000
43/215 Doc ID 018587 Rev 2