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<strong>STM32W108C8</strong><br />
System modules<br />
6.4.3 Event timer<br />
The SysTick timer is an ARM® standard system timer in the NVIC. The SysTick timer can<br />
be clocked from either the FCLK (the clock going into the CPU) or the Sleep Timer clock.<br />
FCLK is either the SCLK or PCLK as selected by CPU_CLK_SEL (see Section 6.3.5: Clock<br />
switching on page 39).<br />
6.4.4 Slow timers (Watchdog and Sleeptimer) control and status registers<br />
Table 8.<br />
These registers are powered from the always-on power domain.<br />
All registers are only writable when in System mode<br />
Watchdog general control register (WDOG_CFG)<br />
Register bits for general top level chip functions and protection.<br />
Watchdog bits can only be written after first writing the appropriate code to the<br />
WDOG_CTRL register.<br />
Address: 0x4000 6000<br />
Reset value: 0x0000 0002<br />
Watchdog general control register (WDOG_CFG)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
WDOG<br />
_DIS<br />
rw<br />
WDOG<br />
_EN<br />
rw<br />
Bit 1 WDOG_DIS: Watchdog disable<br />
Bit 0 WDOG_EN: Watchdog enable<br />
Watchdog control register (WDOG_CTRL)<br />
Requires magic number write to arm the watchdog enable or disable function.<br />
Address: 0x4000 6004<br />
Reset value: 0x0000 0000<br />
Table 9.<br />
Watchdog control register (WDOG_CTRL)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
WDOG_CTRL<br />
w<br />
Doc ID 018587 Rev 2 42/215
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