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System modules<br />
<strong>STM32W108C8</strong><br />
Bit 0 CPU_CLK_SEL: When set to ‘0’, 12-MHz CPU clock is selected. When set to ‘1’, 24-MHz CPU<br />
clock is selected. Note that the clock selection also determines if RAM controller is running at<br />
the same speed as the HCLK (CPU_CLK_SEL = ‘1’) or double speed of HCLK (CPU_CLK_SEL<br />
= ‘0’).<br />
6.4 System timers<br />
6.4.1 Watchdog timer<br />
The <strong>STM32W108C8</strong> integrates a watchdog timer which can be enabled to provide<br />
protection against software crashes and ARM® Cortex-M3 CPU lockup. By default, it is<br />
disabled at power up of the always-on power domain. The watchdog timer uses the<br />
calibrated 1 kHz clock (CLK1K) as its reference and provides a nominal 2.048 s timeout. A<br />
low water mark interrupt occurs at 1.792 s and triggers an NMI to the ARM® Cortex-M3<br />
NVIC as an early warning. When enabled, periodically reset the watchdog timer by writing to<br />
the WDOG_RESTART register before it expires.<br />
The watchdog timer can be paused when the debugger halts the ARM® Cortex-M3. To<br />
enable this functionality, set the bit DBG_PAUSE in the SLEEP_CONFIG register.<br />
If the low-frequency internal RC oscillator (OSCRC) is turned off during deep sleep, CLK1K<br />
stops. As a consequence the watchdog timer stops counting and is effectively paused<br />
during deep sleep.<br />
The watchdog enable/disable bits are protected from accidental change by requiring a two<br />
step process. To enable the watchdog timer the application must first write the enable code<br />
0xEABE to the WDOG_CTRL register and then set the WDOG_EN register bit. To disable<br />
the timer the application must write the disable code 0xDEAD to the WDOG_CTRL register<br />
and then set the WDOG_DIS register bit.<br />
6.4.2 Sleep timer<br />
The <strong>STM32W108C8</strong> integrates a 32-bit timer dedicated to system timing and waking from<br />
sleep at specific times. The sleep timer can use either the calibrated 1 kHz<br />
reference(CLK1K), or the 32 kHz crystal clock (CLK32K). The default clock source is the<br />
internal 1 kHz clock. The sleep timer clock source is chosen with the SLEEPTMR_CLKSEL<br />
register.<br />
The sleep timer has a prescaler, a divider of the form 2^N, where N can be programmed<br />
from 1 to 2^15. This divider allows for very long periods of sleep to be timed. The timer<br />
provides two compare outputs and wrap detection, all of which can be used to generate an<br />
interrupt or a wake up event.<br />
The sleep timer is paused when the debugger halts the ARM® Cortex-M3. No additional<br />
register bit must be set.<br />
To save current during deep sleep, the low-frequency internal RC oscillator (OSCRC) can<br />
be turned off. If OSCRC is turned off during deep sleep and a low-frequency 32.768 kHz<br />
crystal oscillator is not being used, then the sleep timer will not operate during deep sleep<br />
and sleep timer wake events cannot be used to wakeup the <strong>STM32W108C8</strong>.<br />
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