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<strong>STM32W108C8</strong><br />
System modules<br />
In addition to these modes, further automatic control is invoked by hardware when flash<br />
programming is enabled. To ensure accuracy of the flash controller's timers, the FCLK<br />
frequency is forced to 12 MHz during flash programming and erase operations.<br />
Table 5.<br />
System clock modes<br />
f CLK<br />
OSC24M_SEL CPU_CLK_SEL SCLK PCLK<br />
Flash<br />
Program/<br />
Erase Inactive<br />
Flash<br />
Program/<br />
Erase Active<br />
0 (OSCHF) 0 (Normal CPU) 12 MHz 6 MHz 6 MHz 12 MHz<br />
0 (OSCHF) 1 (Fast CPU) 12 MHz 6 MHz 12 MHz 12 MHz<br />
1 (OSC24M) 0 (Normal CPU) 24 MHz 12 MHz 12 MHz 12 MHz<br />
1 (OSC24M) 1 (Fast CPU) 24 MHz 12 MHz 24 MHz 12 MHz<br />
6.3.6 Clock switching registers<br />
Table 6.<br />
XTAL or OSCHF main clock select register (OSC24M_CTRL)<br />
Address offset: 0x4000 401C<br />
Reset value: 0x0000 0000<br />
XTAL or OSCHF main clock select register (OSC24M_CTRL)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
OSC24<br />
M_EN<br />
rws<br />
OSC24<br />
M_SEL<br />
rws<br />
Bit 1 OSC24M_EN: When set to ‘1’, 24 MHz crystal oscillator is main clock.<br />
Bit 0 OSC24M_SEL: When set to ‘0’, OSCHF is selected. When set to ‘1’, XTAL is selected.<br />
Table 7.<br />
CPU clock source select register (CPU_CLK_SEL)<br />
Address offset: 0x4000 4020<br />
Reset value: 0x0000 0000<br />
CPU clock source select register (CPU_CLK_SEL)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Rserved<br />
CPU_C<br />
LK_SEL<br />
rws<br />
Doc ID 018587 Rev 2 40/215
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