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<strong>STM32W108C8</strong><br />
System modules<br />
● PRESETHV Peripheral reset for always-on power domain, for peripherals<br />
that are required to retain their configuration across a deep<br />
sleep cycle.<br />
● PRESETLV Peripheral reset for core power domain, for peripherals that<br />
are not required to retain their configuration across a deep<br />
sleep cycle.<br />
Table 3 shows which reset sources generate certain resets.<br />
Table 3.<br />
Generated resets<br />
Reset source<br />
Reset generation<br />
PORESET SYSRESET DAPRESET PRESETHV PRESETLV<br />
POR HV X X X X X<br />
POR LV (in deep sleep) X X X X<br />
POR LV (not in deep<br />
sleep)<br />
X X X X X<br />
RSTB X X X X<br />
Watchdog reset X X X<br />
Software reset X X X<br />
Option byte error X X X<br />
Normal deep sleep X X X X<br />
Emulated deep sleep X X<br />
Debug reset<br />
X<br />
6.2.4 Reset register<br />
Table 4.<br />
Reset event source register (RESET_EVENT)<br />
Address offset: 0x4000 002C<br />
Reset value: 0x0000 0001<br />
Reset event source register (RESET_EVENT)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
Reserved<br />
CPU_L<br />
OCKU<br />
P<br />
OPT_B<br />
YTE_F<br />
AIL<br />
WAKE_<br />
UP_DS<br />
LEEP<br />
SW_<br />
RST<br />
W_<br />
DOG<br />
RSTB_<br />
PIN<br />
POWE<br />
R_LV<br />
POWE<br />
R_HV<br />
r r r r r r r r<br />
Bit 7 CPU_LOCKUP: When set to ‘1’, the reset is due to core lockup.<br />
Bit 6 OPT_BYTE_FAIL: When set to ‘1’, the reset is due to an Option byte load failure (may be set<br />
with other bits).<br />
Bit 5 WAKE_UP_DSLEEP: When set to ‘1’, the reset is due to a wake-up from Deep Sleep.<br />
Doc ID 018587 Rev 2 36/215
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