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System modules<br />
<strong>STM32W108C8</strong><br />
Deep sleep reset<br />
The Power Management module informs the Reset Generation module of entry into and exit<br />
from the deep sleep states. The deep sleep reset is applied in the following states: before<br />
entry into deep sleep, while removing power from the memory and core domain, while in<br />
deep sleep, while waking from deep sleep, and while reapplying power until reliable power<br />
levels have been detect by POR LV.<br />
The Power Management module allows a special emulated deep sleep state that retains<br />
memory and core domain power while in deep sleep.<br />
6.2.2 Reset recording<br />
Note:<br />
The <strong>STM32W108C8</strong> records the last reset condition that generated a restart to the system.<br />
The reset conditions recorded are:<br />
● POWER_HV Always-on domain power supply failure<br />
● POWER_LV Core or memory domain power supply failure<br />
● RSTB NRST pin asserted<br />
● W_DOG Watchdog timer expired<br />
● SW_RST Software reset by SYSERSETREQ from ARM® Cortex-M3<br />
CPU<br />
● WAKE_UP_DSLEEP Wake-up from deep sleep<br />
● OPT_BYTE_FAIL Error check failed when reading option bytes from Flash<br />
memory<br />
The Reset event source register (RESET_EVENT) is used to read back the last reset event.<br />
All bits are mutually exclusive except the OPT_BYTE_FAIL bit which preserves the original<br />
reset event when set.<br />
While CPU Lockup is marked as a reset condition in software, CPU Lockup is not<br />
specifically a reset event. CPU Lockup is set to indicate that the CPU entered an<br />
unrecoverable exception. Execution stops but a reset is not applied. This is so that a<br />
debugger can interpret the cause of the error. We recommend that in a live application (i.e.<br />
no debugger attached) the watchdog be enabled by default so that the <strong>STM32W108C8</strong> can<br />
be restarted.<br />
6.2.3 Reset generation<br />
The Reset Generation module responds to reset sources and generates the following reset<br />
signals:<br />
● PORESET Reset of the ARM® Cortex-M3 CPU and ARM® Cortex-M3<br />
System Debug components (Flash Patch and Breakpoint,<br />
Data Watchpoint and Trace, Instrumentation Trace Macrocell,<br />
Nested Vectored Interrupt Controller). ARM defines<br />
PORESET as the region that is reset when power is applied.<br />
● SYSRESET Reset of the ARM® Cortex-M3 CPU without resetting the<br />
Core Debug and System Debug components, so that a live<br />
system can be reset without disturbing the debug<br />
configuration.<br />
● DAPRESET Reset to the SWJ's AHB Access Port (AHB-AP).<br />
35/215 Doc ID 018587 Rev 2
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