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<strong>STM32W108C8</strong><br />
System modules<br />
6 System modules<br />
System modules encompass power, resets, clocks, system timers, power management, and<br />
encryption. Figure 4 shows these modules and how they interact.<br />
Figure 4.<br />
System module block diagram<br />
CS YSP WRUPREQ<br />
CDB GPWRUP RE Q<br />
WAKE_CO RE<br />
sleep timer wrap<br />
sleep timer compare a<br />
sleep timer compare b<br />
IRQD<br />
PB2<br />
PA2<br />
GPIO wake monitoring<br />
CLK1K<br />
CLK32K<br />
OSCRC<br />
DIV10<br />
OSC32K<br />
OSC32A<br />
OSC32B<br />
REG_EN<br />
Wakeup Recording<br />
Power Management<br />
deep sleep<br />
wakeup<br />
Sleep Timer<br />
Watchdog<br />
watchdog<br />
VDD_PADS<br />
always-on supply<br />
External<br />
Regulator<br />
recomended<br />
connections for<br />
internal regulator<br />
optional<br />
connections for<br />
external regulator<br />
VREG_OUT<br />
VDD_MEM<br />
VDD_CORE<br />
nRESET<br />
JRST<br />
VREG_1V25<br />
VREG_1V8<br />
Reset Filter<br />
SWJ<br />
POR HV<br />
mem supply<br />
POR LVmem<br />
core supply<br />
POR LVcore<br />
CDBGRSTREQ<br />
POR HV<br />
POR LV<br />
Reset Recording<br />
Reset Generat ion<br />
registers<br />
always-on domain<br />
PRESET HV<br />
RAM<br />
option byte error<br />
SYSRESETREQ<br />
SYSRESET<br />
PORESET<br />
DAPRESET<br />
PRESET LV<br />
registers<br />
AHB-AP<br />
Flash<br />
FLITF<br />
Cortex-M3<br />
CPU<br />
Cortex-M3<br />
Debug<br />
Security Accelerator<br />
SCLK<br />
clock switch<br />
OSCHF<br />
OSC24M<br />
OSCA<br />
OSCB<br />
mem domain<br />
core domain<br />
Doc ID 018587 Rev 2 32/215
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