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STM32W108C8

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<strong>STM32W108C8</strong><br />

Electrical characteristics<br />

Table 144 lists other specifications for the ADC not covered in Table 141, Table 142, and<br />

Table 143.<br />

Table 144.<br />

ADC characteristics<br />

Parameter Min. Typ. Max. Units<br />

VREF 1.17 1.2 1.23 V<br />

VREF output current – – 1 mA<br />

VREF load capacitance – – 10 nF<br />

External VREF voltage range 1.1 1.2 1.3 V<br />

External VREF input impedance 1 – – MΩ<br />

Minimum input voltage<br />

Input buffer disabled<br />

Input buffer enabled<br />

Maximum input voltage<br />

Input buffer disabled<br />

Input buffer enabled<br />

Single-ended signal range<br />

Input buffer disabled<br />

Input buffer enabled<br />

Differential signal range<br />

Input buffer disabled<br />

Input buffer enabled<br />

0<br />

0.1<br />

–<br />

–<br />

0<br />

0.1<br />

-VREF<br />

-VDD_PADS + 0.1<br />

–<br />

–<br />

–<br />

–<br />

–<br />

–<br />

–<br />

–<br />

–<br />

–<br />

VREF<br />

VDD_PADS - 0.1<br />

VREF<br />

VDD_PADS – 0.1<br />

+VREF<br />

+VDD_PADS - 0.1<br />

Common mode range<br />

Input buffer disabled<br />

Input buffer enabled 0 VDD_PADS/2 VREF<br />

Input referred ADC offset -10 – 10 mV<br />

V<br />

V<br />

V<br />

V<br />

V<br />

Input Impedance<br />

1 MHz sample clock<br />

6 MHz sample clock<br />

Not sampling<br />

1<br />

0.5<br />

10<br />

–<br />

–<br />

–<br />

–<br />

–<br />

–<br />

MΩ<br />

Note:<br />

The signal-ended ADC measurements are limited in their range and only guaranteed for<br />

accuracy within the limits shown in this table. The ADC's internal design allows for<br />

measurements outside of this range (±200 mV) when the input buffer is disabled, but the<br />

accuracy of such measurements is not guaranteed. The maximum input voltage is of more<br />

interest to the differential sampling where a differential measurement might be small, but a<br />

common mode can push the actual input voltage on one of the signals towards the upper<br />

voltage limit.<br />

Doc ID 018587 Rev 2 198/215

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