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Electrical characteristics<br />
<strong>STM32W108C8</strong><br />
Table 143 describes the key ADC parameters measured at 25°C and VDD_PADS at 3.0 V,<br />
for a sampling rate of 6 MHz. ADC_HVSELP and ADC_HVSELN are programmed to 1 to<br />
enable the input buffer. The single-ended measurements were done at f input = 7.7% f Nyquist ,<br />
level = 1.2 V p-p swing centered on 1.5 V. The differential measurements were done at<br />
f input =7.7% f Nyquist , level = 1.2 V p-p swing and a comon mode voltage of 1.5 V.<br />
Table 143.<br />
Parameter<br />
ADC module key parameters for input buffer enabled<br />
and 6MHz sampling (1)<br />
Performance<br />
ADC_PERIOD 0 1 2 3 4 5 6 7<br />
Conversion Time (µs) 32 64 128 256 512 1024 2048 4096<br />
Nyquist Freq (kHz) 93.8 46.9 23.4 11.7 5.86 2.93 1.47 0.732<br />
3 dB Cut-off (kHz) 56.6 28.3 14.1 7.07 3.54 1.77k 0.884 0.442<br />
INL (codes peak) 0.055 0.032 0.038 0.07 0.123 0.261 0.522 1.028<br />
INL (codes RMS) 0.028 0.017 0.02 0.04 0.077 0.167 0.326 0.65<br />
DNL (codes peak) 0.028 0.017 0.02 0.04 0.077 0.167 0.326 0.65<br />
DNL (codes RMS) 0.01 0.006 0.006 0.007 0.008 0.013 0.023 0.038<br />
ENOB (from singlecycle<br />
test)<br />
3.6 5.0 6.6 8.1 9.5 10.7 11.3 11.6<br />
SNR (dB)<br />
Single-Ended<br />
Differential<br />
23<br />
23<br />
32<br />
32<br />
41<br />
41<br />
50<br />
50<br />
59<br />
59<br />
65<br />
66<br />
67<br />
69<br />
68<br />
71<br />
SINAD (dB)<br />
Single-Ended<br />
Differential<br />
23<br />
23<br />
32<br />
32<br />
41<br />
41<br />
50<br />
50<br />
58<br />
59<br />
64<br />
66<br />
66<br />
69<br />
66<br />
71<br />
SDFR (dB)<br />
Single-Ended<br />
Differential<br />
48<br />
48<br />
56<br />
57<br />
65<br />
65<br />
72<br />
74<br />
72<br />
82<br />
72<br />
88<br />
73<br />
88<br />
73<br />
88<br />
THD (dB)<br />
Single-Ended<br />
Differential<br />
-33<br />
-33<br />
-42<br />
-42<br />
-51<br />
-51<br />
-59<br />
-60<br />
-66<br />
-69<br />
-68<br />
-76<br />
-68<br />
-80<br />
-68<br />
-82<br />
ENOB (from SNR)<br />
Single-Ended<br />
Differential<br />
3.6<br />
3.6<br />
5.1<br />
5.1<br />
6.6<br />
6.6<br />
8.1<br />
8.1<br />
9.5<br />
9.5<br />
10.5<br />
10.7<br />
10.9<br />
11.3<br />
11<br />
11.5<br />
ENOB (from SINAD)<br />
Single-Ended<br />
Differential<br />
3.6<br />
3.6<br />
5.0<br />
5.1<br />
6.5<br />
6.6<br />
8.0<br />
8.0<br />
9.4<br />
9.5<br />
10.3<br />
10.6<br />
10.7<br />
11.3<br />
10.7<br />
11.4<br />
Equivalent ADC Bits 7 [15:9] 8 [15:8] 9 [15:7]<br />
10<br />
[15:6]<br />
11<br />
[15:5]<br />
12<br />
[15:4]<br />
13<br />
[15:3]<br />
14<br />
[15:2]<br />
1. INL and DNL are referenced to a LSB of the Equivalent ADC Bits shown in the last row of Table 143.<br />
ENOB (effective number of bits) can be calculated from either SNR (signal to non-harmonic noise ratio) or<br />
SINAD (signal-to-noise and distortion ratio).<br />
197/215 Doc ID 018587 Rev 2
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