STM32W108C8

STM32W108C8
Electrical characteristics
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
● A supply overvoltage is applied to each power supply pin
● A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 140.
Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class T A = +105 °C conforming to JESD78A II level A
14.4 ADC characteristics
Table 141 describes the key ADC parameters measured at 25°C and VDD_PADS at 3.0 V,
for a sampling clock of 1 MHz. ADC_HVSELP and ADC_HVSELN are programmed to 0 to
disable the input buffer. The single-ended measurements were done at f input = 7.7% f Nyquist ;
0 dBFS level (where full-scale is a 1.2 V p-p swing). The differential measurements were
done at f input = 7.7% f Nyquist ; -6 dBFS level (where full-scale is a 2.4 V p-p swing).
Table 141. ADC module key parameters for 1 MHz sampling (1)
Parameter
Performance
ADC_PERIOD 0 1 2 3 4 5 6 7
Conversion Time (µs) 32 64 128 256 512 1024 2048 4096
Nyquist Freq (kHz) 15.6 7.81 3.91 1.95 0.977 0.488 0.244 0.122
3 dB Cut-off (kHz) 9.43 4.71 2.36 1.18 0.589 0.295 0.147 0.0737
INL (codes peak) 0.083 0.092 0.163 0.306 0.624 1.229 2.451 4.926
INL (codes RMS) 0.047 0.051 0.093 0.176 0.362 0.719 1.435 2.848
DNL (codes peak) 0.028 0.035 0.038 0.044 0.074 0.113 0.184 0.333
DNL (codes RMS) 0.008 0.009 0.011 0.014 0.019 0.029 0.048 0.079
ENOB (from single-cycle
test)
5.6 7.0 8.6 10.1 11.5 12.6 13.0 13.2
SNR (dB)
Single-Ended
Differential
35
35
44
44
53
53
62
62
70
71
75
77
77
79
77
80
SINAD (dB)
Single-Ended
Differential
35
35
44
44
53
53
61
62
67
70
69
75
70
76
70
76
SDFR (dB)
Single-Ended
Differential
59
60
68
69
72
77
72
80
72
81
72
81
72
81
73
81
Doc ID 018587 Rev 2 194/215