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<strong>STM32W108C8</strong><br />
Interrupts<br />
12.3.6 Top-level missed interrupts register (INT_MISS)<br />
Address: 0x4000 A820<br />
Reset value: 0x0000 0000<br />
Table 129. Top-level missed interrupts register (INT_MISS)<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16<br />
Reserved<br />
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
INT_M<br />
ISSIR<br />
QD<br />
INT_M<br />
ISSIR<br />
QC<br />
INT_M<br />
ISSIR<br />
QB<br />
INT_M<br />
ISSIR<br />
QA<br />
INT_M<br />
ISSAD<br />
C<br />
INT_M<br />
ISSMA<br />
CRX<br />
INT_MI<br />
SSMA<br />
CTX<br />
INT_MI<br />
SSMA<br />
CTMR<br />
INT_MI<br />
SSSE<br />
C<br />
INT_MI<br />
SSSC2<br />
INT_MI<br />
SSSC1<br />
INT_M<br />
ISSSL<br />
EEP<br />
INT_MI<br />
SSBB<br />
INT_MI<br />
SSMG<br />
MT<br />
Reserved<br />
rw rw rw rw rw rw rw rw rw rw rw rw rw rw<br />
Bit 15<br />
Bit 14<br />
Bit 13<br />
Bit 12<br />
Bit 11<br />
Bit 10<br />
Bit 9<br />
Bit 8<br />
Bit 7<br />
Bit 6<br />
Bit 5<br />
Bit 4<br />
Bit 3<br />
Bit 2<br />
INT_MISSIRQD: IRQD interrupt missed.<br />
INT_MISSIRQC: IRQC interrupt missed.<br />
INT_MISSIRQB: IRQB interrupt missed.<br />
INT_MISSIRQA: IRQA interrupt missed.<br />
INT_MISSADC: ADC interrupt missed.<br />
INT_MISSMACRX: MAC receive interrupt missed.<br />
INT_MISSMACTX: MAC transmit interrupt missed.<br />
INT_MISSMACTMR: MAC Timer interrupt missed.<br />
INT_MISSSEC: Security interrupt missed.<br />
INT_MISSSC2: Serial controller 2 interrupt missed.<br />
INT_MISSSC1: Serial controller 1 interrupt missed.<br />
INT_MISSSLEEP: Sleep timer interrupt missed.<br />
INT_MISSBB: Baseband interrupt missed.<br />
INT_MISSMGMT: Management interrupt missed.<br />
Doc ID 018587 Rev 2 186/215
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