STM32W108C8

Interrupts
STM32W108C8
12.3 Nested vectored interrupt controller (NVIC) interrupts
12.3.1 Top-level set interrupts configuration register (INT_CFGSET)
Address: 0xE000E100
Reset value: 0x0000 0000
Table 124. Top-level set interrupts configuration register (INT_CFGSET)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
INT_D
EBUG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_IR
QD
INT_IR
QC
INT_IR
QB
INT_IR
QA
INT_A
DC
INT_M
ACRX
INT_M
ACTX
INT_M
ACTM
R
INT_S
EC
INT_S
C2
INT_S
C1
INT_S
LEEPT
MR
INT_B
B
INT_M
GMT
INT_TI
M2
INT_TI
M1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 16 INT_DEBUG: Write 1 to enable debug interrupt. (Writing 0 has no effect.)
Bit 15 INT_IRQD: Write 1 to enable IRQD interrupt. (Writing 0 has no effect.)
Bit 14 INT_IRQC: Write 1 to enable IRQC interrupt. (Writing 0 has no effect.)
Bit 13 INT_IRQB: Write 1 to enable IRQB interrupt. (Writing 0 has no effect.)
Bit 12 INT_IRQA: Write 1 to enable IRQA interrupt. (Writing 0 has no effect.)
Bit 11 INT_ADC: Write 1 to enable ADC interrupt. (Writing 0 has no effect.)
Bit 10 INT_MACRX: Write 1 to enable MAC receive interrupt. (Writing 0 has no effect.)
Bit 9 INT_MACTX: Write 1 to enable MAC transmit interrupt. (Writing 0 has no effect.)
Bit 8 INT_MACTMR: Write 1 to enable MAC timer interrupt. (Writing 0 has no effect.)
Bit 7 INT_SEC: Write 1 to enable security interrupt. (Writing 0 has no effect.)
Bit 6 INT_SC2: Write 1 to enable serial controller 2 interrupt. (Writing 0 has no effect.)
Bit 5 INT_SC1: Write 1 to enable serial controller 1 interrupt. (Writing 0 has no effect.)
Bit 4 INT_SLEEPTMR: Write 1 to enable sleep timer interrupt. (Writing 0 has no effect.)
Bit 3 INT_BB: Write 1 to enable baseband interrupt. (Writing 0 has no effect.)
Bit 2 INT_MGMT: Write 1 to enable management interrupt. (Writing 0 has no effect.)
Bit 1 INT_TIM2: Write 1 to enable timer 2 interrupt. (Writing 0 has no effect.)
Bit 0 INT_TIM1: Write 1 to enable timer 1 interrupt. (Writing 0 has no effect.)
181/215 Doc ID 018587 Rev 2